Patents by Inventor Michael Christenson
Michael Christenson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11784123Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: GrantFiled: February 22, 2022Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Patent number: 11594673Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.Type: GrantFiled: March 27, 2019Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Noriyuki Sato, Angeline Smith, Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Kevin O'Brien, Benjamin Buford, Tofizur Rahman, Rohan Patil, Nafees Kabir, Michael Christenson, Ian Young, Hui Jae Yoo, Christopher Wiegand
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Publication number: 20220352068Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: ApplicationFiled: June 15, 2022Publication date: November 3, 2022Applicant: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Patent number: 11444024Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: GrantFiled: November 2, 2020Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Publication number: 20220181251Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Publication number: 20220139823Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: ApplicationFiled: November 2, 2020Publication date: May 5, 2022Applicant: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Patent number: 11289421Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: GrantFiled: September 26, 2019Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Publication number: 20210098359Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Applicant: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Publication number: 20200313075Abstract: A memory device includes a first electrode including a spin-orbit material, a magnetic junction on a portion of the first electrode and a first structure including a dielectric on a portion of the first electrode. The first structure has a first sidewall and a second sidewall opposite to the first sidewall. The memory device further includes a second structure on a portion of the first electrode, where the second structure has a sidewall adjacent to the second sidewall of the first structure. The memory device further includes a first conductive interconnect above and coupled with each of the magnetic junction and the second structure and a second conductive interconnect below and coupled with the first electrode, where the second conductive interconnect is laterally distant from the magnetic junction and the second structure.Type: ApplicationFiled: March 27, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Noriyuki SATO, Angeline SMITH, Tanay GOSAVI, Sasikanth MANIPATRUNI, Kaan OGUZ, Kevin O'Brien, Benjamin BUFORD, Tofizur RAHMAN, Rohan PATIL, Nafees KABIR, Michael CHRISTENSON, Ian YOUNG, Hui Jae YOO, Christopher WIEGAND
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Patent number: 7825643Abstract: A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes a master controller and one or more slaves, and the master controller and each slave can communicate using a ring communication scheme. A command generated by the master controller can be passed from the master controller to the subsequent slaves.Type: GrantFiled: April 6, 2009Date of Patent: November 2, 2010Assignee: Volterra Semiconductor CorporationInventors: Andy Burstein, Michael Christenson
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Publication number: 20090189576Abstract: A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes a master controller and one or more slaves, and the master controller and each slave can communicate using a ring communication scheme. A command generated by the master controller can be passed from the master controller to the subsequent slaves.Type: ApplicationFiled: April 6, 2009Publication date: July 30, 2009Applicant: VOLTERRA SEMICONDUCTOR CORPORATIONInventors: Andy Burstein, Michael Christenson
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Patent number: 7514909Abstract: A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes a master controller and one or more slaves, and the master controller and each slave can communicate using a ring communication scheme. A command generated by the master controller can be passed from the master controller to the subsequent slaves.Type: GrantFiled: September 28, 2006Date of Patent: April 7, 2009Assignee: Voiterra Semiconductor CorporationInventors: Andy Burstein, Michael Christenson
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Publication number: 20070075691Abstract: A voltage regulator coupled to an unregulated DC input voltage source by an input terminal, and to a load by an output terminal is disclosed. The voltage regulator converts an input voltage at the input terminal to an output voltage at the output terminal. The voltage regulator includes a master controller and one or more slaves, and the master controller and each slave can communicate using a ring communication scheme. A command generated by the master controller can be passed from the master controller to the subsequent slaves.Type: ApplicationFiled: September 28, 2006Publication date: April 5, 2007Inventors: Andy Burstein, Michael Christenson
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Patent number: 6198261Abstract: A digital control system for a voltage regulator calculates an estimated current representing a current passing through each inductor associated with a switching circuit. A desired total output current is calculated which will maintain an output voltage at the output terminal at a substantially constant level. Upper current limit and a lower current limit are calculated and the switching circuit to is caused couple an input terminal to an output terminal when the estimated current falls below the lower current limit, and caused to couple the output terminal to ground when the estimated current exceeds the upper current limit. Also, the estimated current may be compared to an individual current to trigger the switching circuit.Type: GrantFiled: October 30, 1998Date of Patent: March 6, 2001Assignee: Volterra Semiconductor CorporationInventors: Aaron Schultz, Andrew J. Burstein, Michael Christenson