Patents by Inventor Michael Chudzik
Michael Chudzik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11837683Abstract: Exemplary processing methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The methods may further include forming first, second, and third, gallium-and-nitrogen-containing regions on the nucleation layer. The first gallium-and-nitrogen-containing region may be porosified, without porosifying the second and third gallium-and-nitrogen containing regions. The methods may still further include forming a first active region on the porosified first gallium-and-nitrogen-containing region, and a second active region on the unporosified second gallium-and-nitrogen-containing region. The methods may yet also include forming a third active region on the unporosified third gallium-and-nitrogen-containing region.Type: GrantFiled: March 10, 2021Date of Patent: December 5, 2023Assignee: Applied Materials, Inc.Inventors: Michael Chudzik, Michel Khoury, Max Batres
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Patent number: 11536708Abstract: Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.Type: GrantFiled: January 9, 2020Date of Patent: December 27, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Mark J. Saly, Keenan Navarre Woods, Joseph R. Johnson, Bhaskar Jyoti Bhuyan, William J. Durand, Michael Chudzik, Raghav Sreenivasan, Roger Quon
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Publication number: 20220319836Abstract: Exemplary processing methods include forming a nucleation layer on a substrate. The nucleation layer may be formed by physical vapor deposition (PVD), and the physical vapor deposition may be characterized by a deposition temperature of greater than or about 700° C. The methods may further include forming a patterned mask layer on the nucleation layer. The patterned mask layer may include openings that expose portions of the nucleation layer. Gallium-and-nitrogen-containing regions may be formed on the exposed portions of the nucleation layer. In additional embodiments, the nucleation layer may include a first and second portion separated by an interlayer that stop the propagation of at least some dislocations in the nucleation layer.Type: ApplicationFiled: March 17, 2022Publication date: October 6, 2022Applicant: Applied Materials, Inc.Inventors: Michael Chudzik, Ria Someshwar, Daniel Deyo, Michel Khoury, Sha Zhao
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Publication number: 20220293821Abstract: Exemplary processing methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The methods may further include forming first, second, and third, gallium-and-nitrogen-containing regions on the nucleation layer. The first gallium-and-nitrogen-containing region may be porosified, without porosifying the second and third gallium-and-nitrogen containing regions. The methods may still further include forming a first active region on the porosified first gallium-and-nitrogen-containing region, and a second active region on the unporosified second gallium-and-nitrogen-containing region. The methods may yet also include forming a third active region on the unporosified third gallium- and-nitrogen-containing region.Type: ApplicationFiled: March 10, 2021Publication date: September 15, 2022Applicant: Applied Materials, Inc.Inventors: Michael Chudzik, Michel Khoury, Max Batres
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Publication number: 20220285584Abstract: Exemplary processing methods of forming a semiconductor structure may include forming subpixels on a substrate. Each of the subpixels may include a gallium-and-nitrogen-containing layer formed on an exposed portion of a nucleation layer on the substrate. The subpixels may further include a porosified region formed on or in the gallium-and-nitrogen-containing region, and an active region formed on the porosified region. The active region may include an indium-gallium-and-nitrogen-containing material. The processing methods may further include forming a first reflection layer around one of the subpixels, wherein the first reflection layer includes a first metal layer. The methods may additionally include forming a second reflection layer around another of the subpixels, wherein the second reflection layer includes a second metal that is different than the first metal.Type: ApplicationFiled: March 8, 2021Publication date: September 8, 2022Applicant: Applied Materials, Inc.Inventors: Michel Khoury, Lan Yu, Michael Chudzik, Max Batres
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Publication number: 20220259766Abstract: Exemplary methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The exemplary methods may further include forming at least one gallium nitride (GaN)-containing region on the nucleation layer, and forming an indium-gallium-nitride (InGaN)-containing layer on the GaN-containing region. A porosified region may be formed on a portion of at least one of the GaN-containing region and the InGaN-containing layer, and an active region may be formed on the porosified region. In embodiments, the porosified region may be characterized by a void fraction of greater than or about 20 vol. %. In further embodiments, the active region may include a greater mole percentage (mol. %) indium than the porosified region or the GaN-containing region. In still further embodiments, the active region may characterized by a peak light emission at a wavelength of greater than or about 620 nm.Type: ApplicationFiled: February 16, 2021Publication date: August 18, 2022Applicant: Applied Materials, Inc.Inventors: Michael Chudzik, Max Batres, Michel Khoury
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Patent number: 11410873Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.Type: GrantFiled: November 20, 2020Date of Patent: August 9, 2022Assignee: Applied Materials, Inc.Inventors: Lan Yu, Tyler Sherwood, Michael Chudzik, Siddarth Krishnan
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Publication number: 20220165610Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.Type: ApplicationFiled: November 20, 2020Publication date: May 26, 2022Applicant: Applied Materials, Inc.Inventors: Lan Yu, Tyler Sherwood, Michael Chudzik, Siddarth Krishnan
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Patent number: 11322649Abstract: Exemplary devices may include a substrate, a dielectric layer formed on the substrate, a first light source configured to emit first light characterized by a first wavelength, a second light source configured to emit second light characterized by a second wavelength different from the first wavelength, and a third light source configured to emit third light characterized by a third wavelength different from the first wavelength and the second wavelength. The first light source may be natively formed on a first region of the substrate and arranged within a first opening of the dielectric layer. The second light source may be natively formed on a second region of the substrate and arranged within a second opening of the dielectric layer. The third light source may be natively formed on a third region of the substrate and arranged within a third opening of the dielectric layer.Type: GrantFiled: September 15, 2020Date of Patent: May 3, 2022Assignee: Applied Materials, Inc.Inventors: Michael Chudzik, Errol Antonio C. Sanchez
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Publication number: 20220085238Abstract: Exemplary devices may include a substrate, a dielectric layer formed on the substrate, a first light source configured to emit first light characterized by a first wavelength, a second light source configured to emit second light characterized by a second wavelength different from the first wavelength, and a third light source configured to emit third light characterized by a third wavelength different from the first wavelength and the second wavelength. The first light source may be natively formed on a first region of the substrate and arranged within a first opening of the dielectric layer. The second light source may be natively formed on a second region of the substrate and arranged within a second opening of the dielectric layer. The third light source may be natively formed on a third region of the substrate and arranged within a third opening of the dielectric layer.Type: ApplicationFiled: September 15, 2020Publication date: March 17, 2022Applicant: Applied Materials, Inc.Inventors: Michael Chudzik, Errol Antonio C. Sanchez
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Patent number: 11145761Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.Type: GrantFiled: October 3, 2019Date of Patent: October 12, 2021Assignee: Applied Materials, Inc.Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood, Nam Sung Kim
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Publication number: 20210215664Abstract: Embodiments of the present disclosure provide dual pore sensors and methods for producing these dual pore sensors. The method includes forming a film stack, where the film stack contains two silicon layers and two membrane layers, and then etching the film stack to produce a channel extending therethrough and having two reservoirs and two nanopores. The method also includes depositing a oxide layer on inner surfaces of the reservoirs and nanopores, depositing a dielectric layer on the oxide layer, and forming a metal contact extending through a portion of the stack. The method further includes etching the dielectric layers to form wells, etching the first silicon layer to reveal the protective oxide layer deposited on the inner surfaces of a reservoir, and etching the protective oxide layer deposited on the inner surfaces of the reservoirs and the nanopores.Type: ApplicationFiled: January 9, 2020Publication date: July 15, 2021Inventors: Mark J. SALY, Keenan Navarre WOODS, Joseph R. JOHNSON, Bhaskar Jyoti BHUYAN, William J. DURAND, Michael CHUDZIK, Raghav SREENIVASAN, Roger QUON
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Patent number: 10573719Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.Type: GrantFiled: September 28, 2016Date of Patent: February 25, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Benjamin Colombeau, Michael Chudzik
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Publication number: 20200044152Abstract: Embodiments of methods for depositing doped transition metal oxides are provided herein. In some embodiments, a method of depositing a doped transition metal oxide layer includes: sputtering a first target comprising a transition metal while providing a source of oxygen atoms; sputtering a second target comprising a dopant element; and forming a doped transition metal oxide layer on a substrate from the sputtered transition metal, oxygen atoms, and dopant element. The first target can be formed from a transition metal or a transition metal oxide.Type: ApplicationFiled: July 29, 2019Publication date: February 6, 2020Inventors: MINRUI YU, ANINDITA SEN, VIBHU JINDAL, MICHEL FREI, MAHENDRA PAKALA, MEHUL NAIK, NICOLAS BREIL, MICHAEL CHUDZIK
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Publication number: 20200035822Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.Type: ApplicationFiled: October 3, 2019Publication date: January 30, 2020Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi WOOD, Nam Sung KIM
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Patent number: 10490666Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.Type: GrantFiled: November 6, 2017Date of Patent: November 26, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Shiyu Sun, Nam Sung Kim, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood
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Publication number: 20180061978Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.Type: ApplicationFiled: November 6, 2017Publication date: March 1, 2018Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi Sun WOOD, Nam Sung KIM
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Patent number: 9865735Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.Type: GrantFiled: May 11, 2016Date of Patent: January 9, 2018Assignee: Applied Materials, Inc.Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood, Nam Sung Kim
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Patent number: 9748354Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.Type: GrantFiled: February 15, 2016Date of Patent: August 29, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Wei V. Tang, Paul F. Ma, Steven C. H. Hung, Michael Chudzik, Siddarth Krishnan, Wenyu Zhang, Seshadri Ganguli, Naomi Yoshida, Lin Dong, Yixiong Yang, Liqi Wu, Shih Chung Chen
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Publication number: 20170194430Abstract: The present disclosure provides methods for forming nanowire spacers for nanowire structures with desired materials in horizontal gate-all-around (hGAA) structures for semiconductor chips. In one example, a method of forming nanowire spaces for nanowire structures on a substrate includes performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer, filling the recess with a dielectric material, and removing the dielectric layer over filled from the recess.Type: ApplicationFiled: December 30, 2016Publication date: July 6, 2017Inventors: Bingxi Sun WOOD, Michael G. WARD, Shiyu SUN, Michael CHUDZIK, Nam Sung KIM, Hua CHUNG, Yi-Chiau HUANG, Chentsau YING, Ying ZHANG, Chi-Nung NI, Lin DONG, Dongqing YANG