Patents by Inventor Michael Curtis Parris
Michael Curtis Parris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9557364Abstract: System and method for testing the reliability of a fuse blow condition. The fuse blow detection circuit includes a fuse circuit comprising a fuse having a first end coupled to ground. A common node is coupled to the second end of the fuse. A pre-charge circuit is coupled to the common node for pre-charging the common node to a pre-charged HIGH level. An inverter includes an inverter output and an inverter input, wherein the inverter input is coupled to the common node. A feedback latch is coupled between a voltage source and ground, and includes a latch input that is coupled to the inverter output and a latch output coupled to the common node. A test circuit is included that is coupled to the common node, wherein in a normal mode the test circuit adds strength to the feedback latch for purposes of maintaining the common node at the pre-charged HIGH level, such that in a test mode the feedback latch is weaker than in the normal mode for purposes of maintaining the common node at the pre-charged HIGH level.Type: GrantFiled: May 23, 2014Date of Patent: January 31, 2017Assignee: TESSERA, INC.Inventor: Michael Curtis Parris
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Patent number: 9230814Abstract: Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.Type: GrantFiled: October 28, 2011Date of Patent: January 5, 2016Assignee: INVENSAS CORPORATIONInventors: David Edward Fisch, Michael Curtis Parris
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Patent number: 8970003Abstract: System and method for embedded passive integration relating to a multi-chip packaged device. The packaged device includes a capacitance layer that is configured for electrical coupling to a power supply and to a reference power supply. Further, the capacitance layer is configured for filtering the power supply and providing a filtered power supply. A semiconductor layer including a logic device is configured for electrical coupling to the filtered power supply.Type: GrantFiled: July 29, 2011Date of Patent: March 3, 2015Assignee: Tessera, Inc.Inventor: Michael Curtis Parris
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Patent number: 8873302Abstract: An array of memory cells, in which one or more memory cells have a common doped region. Each memory cell includes a transistor with a floating gate, source and drain regions, and separate gate and drain voltage controls. Each memory cell also includes a coupling capacitor electrically coupled to and located laterally from the floating gate. In the array, first bit lines are oriented in a first direction, wherein a first bit line is coupled to drain regions of transistors that are arranged in a column. The array includes second bit lines also oriented in the first direction, wherein a second bit line is coupled to source regions of transistors that are arranged in a column. The array also includes word lines oriented in a second direction, wherein each word line is coupled to control gates of coupling capacitors that are arranged in a row.Type: GrantFiled: October 28, 2011Date of Patent: October 28, 2014Assignee: Invensas CorporationInventors: David Edward Fisch, William C. Plants, Michael Curtis Parris
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Publication number: 20140253145Abstract: System and method for testing the reliability of a fuse blow condition. The fuse blow detection circuit includes a fuse circuit comprising a fuse having a first end coupled to ground. A common node is coupled to the second end of the fuse. A pre-charge circuit is coupled to the common node for pre-charging the common node to a pre-charged HIGH level. An inverter includes an inverter output and an inverter input, wherein the inverter input is coupled to the common node. A feedback latch is coupled between a voltage source and ground, and includes a latch input that is coupled to the inverter output and a latch output coupled to the common node. A test circuit is included that is coupled to the common node, wherein in a normal mode the test circuit adds strength to the feedback latch for purposes of maintaining the common node at the pre-charged HIGH level, such that in a test mode the feedback latch is weaker than in the normal mode for purposes of maintaining the common node at the pre-charged HIGH level.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: TESSERA, INC.Inventor: Michael Curtis Parris
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Patent number: 8736278Abstract: System and method for testing the reliability of a fuse blow condition. The fuse blow detection circuit includes a fuse circuit comprising a fuse having a first end coupled to ground. A common node is coupled to the second end of the fuse. A pre-charge circuit is coupled to the common node for pre-charging the common node to a pre-charged HIGH level. An inverter includes an inverter output and an inverter input, wherein the inverter input is coupled to the common node. A feedback latch is coupled between a voltage source and ground, and includes a latch input that is coupled to the inverter output and a latch output coupled to the common node. A test circuit is included that is coupled to the common node, wherein in a normal mode the test circuit adds strength to the feedback latch for purposes of maintaining the common node at the pre-charged HIGH level, such that in a test mode the feedback latch is weaker than in the normal mode for purposes of maintaining the common node at the pre-charged HIGH level.Type: GrantFiled: July 29, 2011Date of Patent: May 27, 2014Assignee: Tessera Inc.Inventor: Michael Curtis Parris
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Publication number: 20130107635Abstract: An array of memory cells, in which one or more memory cells have a common doped region. Each memory cell includes a transistor with a floating gate, source and drain regions, and separate gate and drain voltage controls. Each memory cell also includes a coupling capacitor electrically coupled to and located laterally from the floating gate. In the array, first bit lines are oriented in a first direction, wherein a first bit line is coupled to drain regions of transistors that are arranged in a column. The array includes second bit lines also oriented in the first direction, wherein a second bit line is coupled to source regions of transistors that are arranged in a column. The array also includes word lines oriented in a second direction, wherein each word line is coupled to control gates of coupling capacitors that are arranged in a row.Type: ApplicationFiled: October 28, 2011Publication date: May 2, 2013Applicant: INVENSAS CORPORATIONInventors: David Edward Fisch, William C. Plants, Michael Curtis Parris
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Publication number: 20130107630Abstract: Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.Type: ApplicationFiled: October 28, 2011Publication date: May 2, 2013Applicant: INVENSAS CORPORATIONInventors: David Edward Fisch, Michael Curtis Parris
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Publication number: 20130027899Abstract: System and method for embedded passive integration relating to a multi-chip packaged device. The packaged device includes a capacitance layer that is configured for electrical coupling to a power supply and to a reference power supply. Further, the capacitance layer is configured for filtering the power supply and providing a filtered power supply. A semiconductor layer including a logic device is configured for electrical coupling to the filtered power supply.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: TESSERA, INC.Inventor: Michael Curtis Parris
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Publication number: 20130027056Abstract: System and method for testing the reliability of a fuse blow condition. The fuse blow detection circuit includes a fuse circuit comprising a fuse having a first end coupled to ground. A common node is coupled to the second end of the fuse. A pre-charge circuit is coupled to the common node for pre-charging the common node to a pre-charged HIGH level. An inverter includes an inverter output and an inverter input, wherein the inverter input is coupled to the common node. A feedback latch is coupled between a voltage source and ground, and includes a latch input that is coupled to the inverter output and a latch output coupled to the common node. A test circuit is included that is coupled to the common node, wherein in a normal mode the test circuit adds strength to the feedback latch for purposes of maintaining the common node at the pre-charged HIGH level, such that in a test mode the feedback latch is weaker than in the normal mode for purposes of maintaining the common node at the pre-charged HIGH level.Type: ApplicationFiled: July 29, 2011Publication date: January 31, 2013Applicant: TESSERA INC.Inventor: Michael Curtis Parris
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Patent number: 6549470Abstract: A small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays which advantageously utilizes non-precharged data lines and reduced output voltage swing to reduce power requirements, tri-stateable outputs to allow several circuits to be multiplexed on the same data line and provides a buffer between the sense amplifier and the data lines to improve data line switching speed.Type: GrantFiled: August 17, 2001Date of Patent: April 15, 2003Assignees: United Memories, Inc., Sony CorporationInventors: Kim Carver Hardee, Michael Curtis Parris
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Publication number: 20020136051Abstract: A small signal, low power read data bus driver for integrated circuit devices incorporating memory arrays which advantageously utilizes non-precharged data lines and reduced output voltage swing to reduce power requirements, tri-stateable outputs to allow several circuits to be multiplexed on the same data line and provides a buffer between the sense amplifier and the data lines to improve data line switching speed.Type: ApplicationFiled: August 17, 2001Publication date: September 26, 2002Inventors: Kim Carver Hardee, Michael Curtis Parris