Patents by Inventor Michael D. Fitzsimmons
Michael D. Fitzsimmons has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7725788Abstract: A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.Type: GrantFiled: January 25, 2007Date of Patent: May 25, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Thomas Tkacik, John E. Spittal, Jr., Jonathan Lutz, Lawrence Case, Douglas Hardy, Mark Redman, Gregory Schmidt, Steven Tugenberg, Michael D. Fitzsimmons, Darrell L. Carder
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Patent number: 7500152Abstract: A system and method time orders events that occur in various portions of the system (10) where different time domains (12, 22, 32) exist. Timestamping circuitry (e.g. 40) is provided in each of a plurality of functional circuits or modules (14, 24, 34). The timestamping circuitry provides a message that indicates a point in time when a predetermined event occurs. An interface module (70) is coupled to each of the plurality of functional circuits (14, 24, 34). The interface module (70) provides control information to the plurality of functional circuits (14, 24, 34) to indicate at least one operating condition that triggers the predetermined event, and to optionally specify a message format. The interface module (70) provides a timestamping message from one, several or all time domains at a common interface port (90).Type: GrantFiled: December 5, 2003Date of Patent: March 3, 2009Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Richard G. Collins, Michael D. Fitzsimmons, Jason T. Nearing
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Patent number: 7404019Abstract: A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect the endianness order of the information transferred during the access. In one embodiment, the first endianness control overrides a default endianness corresponding to the access. The default endianness may be provided by a master endianness control corresponding to a master requesting the current access. A data processing system includes a first bus master, first and second peripherals, first endianness control corresponding to the first peripheral and second endianness control corresponding to the second peripheral, and control circuitry which uses the first endianness control to control endianness for an access between the first bus master and the first peripheral. In one embodiment, the data processing system may include multiple masters.Type: GrantFiled: May 26, 2004Date of Patent: July 22, 2008Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Michael D. Fitzsimmons
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Patent number: 7353311Abstract: A method is disclosed whereby a priority amongst transactions capable of being processed at a common time is determined based upon a transaction identifier associated with each of the transaction. The transaction identifier can either directly indicate a priority amongst the transactions, or use to index storage locations that indicate priority values. The transaction identifiers can be selected to be associated with a transaction by the requesting device or other priority determination module based upon predefined criteria.Type: GrantFiled: June 1, 2005Date of Patent: April 1, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Brett W. Murdock, William C. Moyer, Michael D. Fitzsimmons
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Patent number: 7278062Abstract: In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.Type: GrantFiled: January 9, 2003Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Michael D. Fitzsimmons, Brian M. Millar, John J. Vaglica
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Patent number: 7277972Abstract: One embodiment of the present invention provides a flexible peripheral access protection mechanism within a data processing system (10) in order to obtain a more secure operating environment. For example, the data processing system may include a combination of secure (12) and unsecure bus masters (14, 15) needing to access shared peripherals (22, 24). One embodiment allows for the dynamic update by a secure bus master (12) of access permissions corresponding to each unsecure bus master for each peripheral. A secure bus master is therefore able to establish which unsecure bus masters have permission to access which peripheral in order to protect the data processing system from corruption due to errant or hostile software running on unsecure bus masters. Through the use of a bus master identifier (36), access to the requested peripheral is either allowed or denied based on the permissions established by the secure bus master.Type: GrantFiled: March 8, 2002Date of Patent: October 2, 2007Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Michael D. Fitzsimmons
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Patent number: 7266848Abstract: The invention relates to an integrated circuit (IC), and more particularly to security to protect an IC (10) against unauthorized accesses. In one embodiment, an identifier is provided external to IC 10. A corresponding input IC security key (52) is then provided to IC 10 and compared to a stored IC security key (30). If the input IC security key (52) and the stored IC security key (30) do not match, access to protected functional circuitry (12) is prohibited. The present invention may use any debug interface, including standard debug interfaces using the JTAG 1149.1 interface defined by the IEEE.Type: GrantFiled: March 18, 2002Date of Patent: September 4, 2007Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Michael D. Fitzsimmons
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Patent number: 7185121Abstract: A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port control circuitry (48), configuration registers (46) and slave port arbiter logic (34, 36, 38, 40, 42 and 44) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.Type: GrantFiled: August 15, 2005Date of Patent: February 27, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Michael D. Fitzsimmons, William C. Moyer, Brett W. Murdock
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Patent number: 7185249Abstract: A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.Type: GrantFiled: April 30, 2002Date of Patent: February 27, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Thomas Tkacik, John E. Spittal, Jr., Jonathan Lutz, Lawrence Case, Douglas Hardy, Mark Redman, Gregory Schmidt, Steven Tugeberg, Michael D. Fitzsimmons, Darrell L. Carder
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Patent number: 7155618Abstract: Systems and methods are discussed to identify a recoverable state in a low power device. A low power device having an arbiter to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller within the low power device provides a request to the bus arbiter to initiate a low power mode. The bus arbiter stops granting bus requests to the bus masters and identifies when the system bus has processed all current bus accesses. When the system bus is idle, the bus arbiter returns a bus grant signal to the low power controller. Clocks associated with the bus masters are disabled to suspend the bus arbiters and allow less power to be consumed by the low power device.Type: GrantFiled: March 8, 2002Date of Patent: December 26, 2006Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Brian M. Millar, Michael D. Fitzsimmons
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Patent number: 7099973Abstract: A system (100) having a plurality of bus masters (111–113) coupled to an arbiter (150) is disclosed. An arbiter (150) is coupled to a first storage location (151) and a second storage location (152), where the first and second storage locations store bus master parking information for a system bus (141). The arbiter (150) receives a parking context indicator (131) that is used to select one of the first and second storage locations (151, 152) to provide bus master parking information to the arbiter (150).Type: GrantFiled: March 26, 2003Date of Patent: August 29, 2006Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Michael D. Fitzsimmons, Brett W. Murdock
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Patent number: 6954821Abstract: A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port control circuitry (48), configuration registers (46) and slave port arbiter logic (34, 36, 38, 40, 42 and 44) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.Type: GrantFiled: July 31, 2003Date of Patent: October 11, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Michael D. Fitzsimmons, William C. Moyer, Brett W. Murdock
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Publication number: 20040221173Abstract: A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect the endianness order of the information transferred during the access. In one embodiment, the first endianness control overrides a default endianness corresponding to the access. The default endianness may be provided by a master endianness control corresponding to a master requesting the current access. A data processing system includes a first bus master, first and second peripherals, first endianness control corresponding to the first peripheral and second endianness control corresponding to the second peripheral, and control circuitry which uses the first endianness control to control endianness for an access between the first bus master and the first peripheral. In one embodiment, the data processing system may include multiple masters.Type: ApplicationFiled: May 26, 2004Publication date: November 4, 2004Inventors: William C. Moyer, Michael D. Fitzsimmons
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Publication number: 20040193766Abstract: A system (100) having a plurality of bus masters (111-113) coupled to an arbiter (150) is disclosed. An arbiter (150) is coupled to a first storage location (151) and a second storage location (152), where the first and second storage locations store bus master parking information for a system bus (141). The arbiter (150) receives a parking context indicator (131) that is used to select one of the first and second storage locations (151, 152) to provide bus master parking information to the arbiter (150).Type: ApplicationFiled: March 26, 2003Publication date: September 30, 2004Inventors: William C. Moyer, Michael D. Fitzsimmons, Brett W. Murdock
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Patent number: 6769076Abstract: A real-time processor debug system that selectively samples address and data signals of a virtual bus of a core processor during real-time operations to reduce power consumption and to minimize performance impact due to bus loading. Gating logic for an embedded processor provides the virtual bus signals of a core processor, including address and data signals, to a debug interface of an embedded system chip or integrated circuit (IC). The gating logic receives update data and update address signals from the debug interface to control switching on corresponding debug address and data buses. The core processor provides processor status signals to the debug interface so that the debug interface determines the particular transaction being performed by the core processor. The processor status signals indicate change of flow (COF) events as well as instruction fetch or data fetch cycles.Type: GrantFiled: February 7, 2000Date of Patent: July 27, 2004Assignee: Freescale Semiconductor, Inc.Inventors: William C. Moyer, Michael D. Fitzsimmons, Richard G. Collins
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Publication number: 20040139372Abstract: In one embodiment, a data processing system (10) has a processor (14) coupled to a bus, where the data processing system (10) includes access error detection circuitry (26) and access error response circuitry (12), each coupled to the bus (58, 60). The access error detection circuitry detects an access error in the data processing system. The access error response circuitry initiates replacement of an existing value on the bus with a predetermined value when the access error has been detected, and continues to replace the existing value on the bus with the predetermined value when the access error has been detected and a persistent mode indicator has been asserted. The predetermined value may correspond to a predetermined instruction value (74) or a predetermined data value (76). In one embodiment, different values for the predetermined value may be used depending on the current operating mode of the data processing system.Type: ApplicationFiled: January 9, 2003Publication date: July 15, 2004Inventors: William C. Moyer, Michael D. Fitzsimmons, Brian M. Millar, John J. Vaglica
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Publication number: 20030204801Abstract: A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.Type: ApplicationFiled: April 30, 2002Publication date: October 30, 2003Applicant: Motorola, Inc.Inventors: Thomas Tkacik, John E. Spittal, Jonathan Lutz, Lawrence Case, Douglas Hardy, Mark Redman, Gregory Schmidt, Steven Tugeberg, Michael D. Fitzsimmons, Darrell L. Carder
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Patent number: 6625727Abstract: A data processing system (400) is configured when coming out of reset using memories of various bit widths (440, 450, 460). The bytes that make up the reset vector (300) are fetched individually through separate memory operations from the memory that stores the reset vector. These bytes are stored in a pre-determined manner within each of the potential memory structures (440, 450, 460) such that predetermined addresses will retrieve the different bytes on the same portion of the data bus. A configuration value (310) portion of the reset vector (300) retrieved may be used to configure various parameters (352-356, 362) within the data processing system (400) such that parameters related to the memory or other functional characteristics of the system are initialized. The configuration value (310) may include data and control sections such that the control section determines how the data section of the configuration value (310) is applied to various parameters within the data processing system (400).Type: GrantFiled: November 23, 1999Date of Patent: September 23, 2003Assignee: Motorola, Inc.Inventors: William C. Moyer, Michael D. Fitzsimmons, James C. Nash
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Publication number: 20030177373Abstract: The invention relates to an integrated circuit (IC), and more particularly to security to protect an IC (10) against unauthorized accesses. In one embodiment, an identifier is provided external to IC 10. A corresponding input IC security key (52) is then provided to IC 10 and compared to a stored IC security key (30). If the input IC security key (52) and the stored IC security key (30) do not match, access to protected functional circuitry (12) is prohibited. The present invention may use any debug interface, including standard debug interfaces using the JTAG 1149.1 interface defined by the IEEE.Type: ApplicationFiled: March 18, 2002Publication date: September 18, 2003Inventors: William C. Moyer, Michael D. Fitzsimmons
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Publication number: 20030172310Abstract: Systems and methods are discussed to identify a recoverable state in a low power device. A low power device having an arbiter to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller within the low power device provides a request to the bus arbiter to initiate a low power mode. The bus arbiter stops granting bus requests to the bus masters and identifies when the system bus has processed all current bus accesses. When the system bus is idle, the bus arbiter returns a bus grant signal to the low power controller. Clocks associated with the bus masters are disabled to suspend the bus arbiters and allow less power to be consumed by the low power device.Type: ApplicationFiled: March 8, 2002Publication date: September 11, 2003Inventors: William C. Moyer, Brian M. Millar, Michael D. Fitzsimmons