Patents by Inventor Michael D. Goodner

Michael D. Goodner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8992806
    Abstract: An absorbing composition is described herein that includes at least one inorganic-based compound, at least one absorbing compound, and at least one material modification agent. In addition, methods of making an absorbing composition are also described that includes: a) combining at least one inorganic-based compound, at least one absorbing compound, at least one material modification agent, an acid/water mixture, and one or more solvents to form a reaction mixture; and b) allowing the reaction mixture to form the absorbing composition at room temperature. Another method of making an absorbing composition includes: a) combining at least one inorganic-based compound, at least one absorbing compound, at least one material modification agent, an acid/water mixture, and one or more solvents to form a reaction mixture; and b) heating the reaction mixture to form the absorbing composition.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: March 31, 2015
    Assignee: Honeywell International Inc.
    Inventors: Bo Li, Joseph Kennedy, Nancy Iwamoto, Mark A. Fradkin, Makarem A. Hussein, Michael D. Goodner, Victor Lu, Roger Leung
  • Patent number: 8513111
    Abstract: A semiconductor structure may be covered with a thermally decomposing film. That film may then be covered by a sealing cover. Subsequently, the thermally decomposing material may be decomposed, forming a cavity.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Robert P. Meagley, Kevin P. O'Brien, Tian-An Chen, Michael D. Goodner, James Powers, Huey-Chiang Liou
  • Patent number: 8104172
    Abstract: Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: January 31, 2012
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Kevin J. Lee
  • Patent number: 8053159
    Abstract: An absorbing composition is described herein that includes at least one inorganic-based compound, at least one absorbing compound, and at least one material modification agent. In addition, methods of making an absorbing composition are also described that includes: a) combining at least one inorganic-based compound, at least one absorbing compound, at least one material modification agent, and one or more solvents to form a reaction mixture, wherein the at least one material modification agent comprises at least one acid and water; and b) heating the reaction mixture to form an absorbing material, a coating or a film.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: November 8, 2011
    Assignee: Honeywell International Inc.
    Inventors: Bo Li, Joseph Kennedy, Nancy Iwamoto, Victor Lu, Roger Leung, Mark A. Fradkin, Makarem A. Hussein, Michael D. Goodner
  • Patent number: 8003293
    Abstract: A deliberately engineered placement and size constraint (molecular weight distribution) of photoacid generators, solubility switches, photoimageable species, and quenchers forms individual pixels within a photoresist. Upon irradiation, a self-contained reaction occurs within each of the individual pixels that were irradiated to pattern the photoresist. These pixels may take on a variety of forms including a polymer chain, a bulky cluster, a micelle, or a micelle formed of several polymer chains. Furthermore, these pixels may be designed to self-assemble onto the substrate on which the photoresist is applied.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: August 23, 2011
    Assignee: Intel Corporation
    Inventors: Robert P. Meagley, Michael D. Goodner, Bob E. Leet, Michael L. McSwiney
  • Patent number: 7790630
    Abstract: A silicone-doped carbon interlayer dielectric (ILD) and its method of formation are disclosed. The ILD's dielectric constant and/or its mechanical strength can be tailored by varying the ratio of carbon-to-silicon in the silicon-doped carbon matrix.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: September 7, 2010
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, George A. Antonelli
  • Publication number: 20100210072
    Abstract: Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein.
    Type: Application
    Filed: April 21, 2010
    Publication date: August 19, 2010
    Applicant: Intel Corporation
    Inventors: Michael D. Goodner, Kevin J. Lee
  • Patent number: 7732936
    Abstract: Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein, wherein the buffer coating is provided by mechanically blending a first polymer with at least a second polymer. The mechanically blended polymers producing a buffer coating that provides a barrier that is has an increased toughness and decreased shrinkage.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: June 8, 2010
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Kevin J. Lee
  • Patent number: 7658975
    Abstract: Method and structure for minimizing the downsides associated with microelectronic device processing adjacent porous dielectric materials are disclosed. In particular, chemical protocols are disclosed wherein porous dielectric materials may be sealed by attaching coupling agents to the surfaces of pores. The coupling agents may form all or part of caps on reactive groups in the dielectric surface or may crosslink to seal pores in the dielectric.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: February 9, 2010
    Assignee: Intel Corporation
    Inventors: Grant Kloster, Robert P. Meagley, Michael D. Goodner, Kevin P. O'brien
  • Patent number: 7615337
    Abstract: A cap may be formed anisotropically over a photoresist feature. For example, a material, such as a polymer, may be coated over the photoresist feature. If the coated material is photoactive, the cap may be grown preferentially in the vertical direction, creating high aspect ratio structures in some embodiments of the present invention.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: November 10, 2009
    Assignee: Intel Corporation
    Inventors: Robert P. Meagley, Michael McSwiney, Michael D. Goodner, Robert Leet, Manish Chandhok
  • Patent number: 7595555
    Abstract: A method of forming air gaps surrounding conductors in a dielectric layer, the dielectric layer comprising, for example, part of the interconnect structure of an integrated circuit device. The air gaps are formed, in part, by depositing a sacrificial material within a trench and/or via that have been formed in a dielectric layer, and the sacrificial material is ultimately removed after metal deposition to create the air gaps. A porous dielectric cap may be deposited over the dielectric layer, and the sacrificial material may be removed through this porous dielectric layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: September 29, 2009
    Assignee: Intel Corporation
    Inventors: James S. Clarke, Michael D. Goodner
  • Patent number: 7585615
    Abstract: A composite photoresist comprises a photoresist material and a filler material dispersed within the photoresist material, wherein the filler material includes a plurality of nanoparticles. The photoresist material may comprise an acrylic-based photoresist, a novolak-based photoresist, a polyhydroxystyrene-based photoresist, a SLAM, or a BARC. The filler material may comprise base-soluble styrene-butadiene rubber nanospheres, nitrile-butadiene rubber nanospheres, polystyrene-based nanoparticles, acrylic-based nanoparticles, or inorganic nanoparticles. The nanoparticles may have an average diameter that is between around 10 nm and around 1000 nm and may have a loading in the photoresist material that is between around 5% and 50%. The composite photoresist may be used to form die-side metal bumps for use in a C4 connection that have a roughened sidewall surface but a smooth top surface.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: September 8, 2009
    Assignee: Intel Corporation
    Inventors: Kurt Schultz, Kevin J. Lee, Michael D. Goodner, Shane Nolen
  • Patent number: 7572732
    Abstract: Several techniques are described for modulating the etch rate of a sacrificial light absorbing material (SLAM) by altering its composition so that it matches the etch rate of a surrounding dielectric. This particularly useful in a dual damascene process where the SLAM fills a via opening and is etched along with a surrounding dielectric material to form trenches overlying the via opening.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: August 11, 2009
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Robert P. Meagley, Kevin P. O'Brien
  • Patent number: 7563727
    Abstract: A method for forming a high mechanical strength, low k, interlayer dielectric material with aluminosilicate precursors so that aluminum is facilely incorporated into the silicon matrix of the material, and an integrated circuit device comprising one or more high-strength, low-k interlayer dielectric layers so formed.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: July 21, 2009
    Assignee: Intel Corporation
    Inventor: Michael D. Goodner
  • Patent number: 7560165
    Abstract: Method and structure for minimizing the downsides associated with microelectronic device processing adjacent porous dielectric materials are disclosed. In particular, chemical protocols are disclosed wherein porous dielectric materials may besealed by attaching coupling agents to the surfaces of pores. The coupling agents may form all or part of caps on reactive groups in the dielectric surface or may crosslink to seal pores in the dielectric.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: July 14, 2009
    Assignee: Intel Corporation
    Inventors: Grant Kloster, Robert P. Meagley, Michael D. Goodner, Kevin P. O'brien, Don Bruner
  • Publication number: 20090133908
    Abstract: An interconnect structure for a microelectronic device includes an electrically conductive material (130, 730, 930) adjacent to a metallization layer (120, 320, 920). The electrically conductive material has a base (131, 931) and a body (132, 932). The base is wider than the body. The base and the body form a single monolithic structure having no internal interface. The interconnect structure may be manufactured by providing a substrate (110, 310, 910) to which the metallization layer is applied, forming a sacrificial layer (410) adjacent to the metallization layer and a resist layer (510) adjacent to the sacrificial layer, patterning the resist layer to form an opening (610) (thereby removing a portion of the sacrificial layer), placing the electrically conductive material in the opening, and removing the resist layer, the sacrificial layer, and a portion of the metallization layer.
    Type: Application
    Filed: November 28, 2007
    Publication date: May 28, 2009
    Inventors: Michael D. Goodner, Kevin J. Lee
  • Patent number: 7470450
    Abstract: A silicon nitride film may be deposited on a work piece using conventional deposition techniques and a selected source for use as a silicon precursor. A nitrogen precursor may also be selected for film deposition. Using the selected precursor(s), the temperature for deposition may be 500° C., or less.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Michael L. McSwiney, Mansour Moinpour, Michael D. Goodner
  • Patent number: 7466025
    Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer comprising a porous matrix, as well as a porogen in certain variations, is formed adjacent a sacrificial dielectric layer. Subsequent to other processing treatments, a portion of the sacrificial dielectric layer is decomposed and removed through a portion of the porous matrix using supercritical carbon dioxide leaving voids in positions previously occupied by portions of the sacrificial dielectric layer. The resultant structure has a desirably low k value as a result of the voids and materials comprising the porous matrix and other structures. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.
    Type: Grant
    Filed: April 14, 2005
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Jihperng Leu
  • Patent number: 7452728
    Abstract: Methods and systems for the concentration and removal of metal ions from aqueous solutions are described, comprising treating the aqueous solutions with photoswitchable ionophores.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: November 18, 2008
    Assignee: Intel Corporation
    Inventors: Bob E. Leet, Robert P. Meagley, Michael D. Goodner, Michael L. McSwiney
  • Patent number: 7439179
    Abstract: A method for healing detrimental bonds in deposited materials, for example porous, low-k dielectric materials, including oxydatively processing a deposited material, processing the deposited material with a trialkyl group III compound, and processing in the presence of an alcohol. Also included in embodiments of the invention are materials with bonds healed by embodiments of the claimed method.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: October 21, 2008
    Assignee: Intel Corporation
    Inventor: Michael D. Goodner