Abstract: A hammer timing control system for a line printer has a register for storing a digital delay value related to the actual flight time of a controlled print hammer. A delay counter activated by an initiate fire pulse counts timing pulses until the count equals the delay value in the register. A comparator generates a fire signal when the count equals the delay value in the register. The counter continues counting pulses to a second count whereupon the fire signal is terminated. The second count is either decoded or compared with a predetermined quantity in a second register to terminate the fire signal. The counter may also be an up/down counter which counts up to delay and down to terminate the fire signal. Delay values can be stored in an external memory device such as a magnetic disk for transfer to the individual registers for each of the print hammers.

Abstract: The control system for a line printer includes compensation circuit means for electronically changing the timing of the reference or home pulse to compensate for changes in the speed of the type characters on a continuous type carrier. The compensation circuit includes a storage register, a counter and a comparison circuit for comparing the content of the storage register and the counter. The counter when activated by a reference pulse generated from a reference mark on the moving type carrier counts subscan pulses generated from timing marks moving with the type characters. The storage register, which is programmable, stores different numeric values dependent on the speed of the type carrier representing different numbers of subscan pulses to be counted by the counter means. The comparator circuit compares the numeric value in the register with the count registered in the counting means.

Abstract: A method and apparatus for testing print elements of a printer, such as a belt printer, in which the print element operating circuits are energized at an energy level insufficient to cause printing but sufficient to generate feedback signals for checking operativeness by a microprocessor.