Abstract: A parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an interconnector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.

Abstract: A parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an interconnector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.

Abstract: A parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an interconnector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.

Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

Abstract: A method of testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip test fixture system is provided. The chip test fixture system has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into electrically conductive contact with the conductor pads on the chip test fixture system. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing the chip is removed from the substrate.