Abstract: A method and apparatus for performing fast clip-testing operations in a general purpose processor are provided. This is accomplished by executing a single instruction for comparing a first value x to a second value y and, as a result of the comparison, determining whether x is less than y and whether x-is less than negative y. The values x and y are stored in respective source registers of the processor specified by the instruction. Finally, as a result of the determination, one or more binary values representing the results of the determination are inserted into a destination register of the processor also specified by the instruction. Accordingly, the invention advantageously provides a general purpose processor with the ability to execute a clip-testing function with a single instruction compared with prior art general purpose processors that require multiple instructions to perform the same function.

Abstract: A photon-based model of individual cones in the human eye perceiving images on digital display devices is presented. Playback of streams of pixel video data is modeled as individual photon emission events from within the physical substructure of each display pixel. The generated electromagnetic wavefronts are refracted through a four surface model of the human cornea and lens, and diffracted at the pupil. The characteristics of each of several million photoreceptor cones in the retina are individually modeled by a synthetic retina model. Photon absorption events map the collapsing wavefront to photon detection events in a particular cone, resulting in images of the photon counts in the retinal cone array. The rendering systems used to generate sequences of these images account for wavelength dependent absorption in the tissues of the eye and the motion blur caused by slight movement of the eye during a frame of viewing.

Abstract: A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Abstract: An apparatus and method for splitting vertex streams relating to graphics data into substreams, and processing the substreams in parallel. A graphics subsystem of a computer system includes a vertex splitting module, which determines whether incoming vertex streams are of a unicast, unlocked type, and thus available for splitting, and further whether graphics primitives in the vertex stream are of a type that may be split. If appropriate, the vertex splitting module then locates vertices in the vertex stream, generates substreams from the vertex stream, and transmits the substreams in a load-balanced operation to multiple graphics processors for parallel processing and outputting to an output device. If the vertex stream is too large to store in FIFO queues of the graphics processors, it is not split into substreams.

Abstract: A lightweight detachable air coupler for an air seeder comprises an aluminum frame having two steel sleeves die cast into the frame. The frame is provided with two circular apertures each being defined by a rim having an internal cylindrical surface. The steel cylindrical sleeve has a first end having an exterior surface that is diagonally knurled. Two steel sleeves are mounted in the mold for the aluminum frame and cast aluminum is injected into the mold. The liquid aluminum adheres to the knurled exterior surface of the steel sleeves. The aluminum frame has a front surface from which the rims project and a rear surface from which the sleeves project.

Abstract: A graphics system comprises a rendering unit, a sample buffer, and a sample-to-pixel calculation unit. The rendering unit receives vertices defining a triangle, and generates first and second octant identifier words for first and second edges of the triangle respectively. In most cases, the two octant identifier words determine the triangle orientation. However, in a few special cases (i.e. when the octant identifier words specify the same or opposite octants), the triangle orientation is resolved based on a comparison of the slopes of the first and second edge. Further rendering operations on the triangle may be conditioned on the value of the triangle orientation. The triangle orientation may be used to determine the interior side of each triangle edge. Sample positions falling on the interior side of all three edges are labeled as interior samples. Color values are computed for interior samples.

Abstract: A clip testing unit within a graphics accelerator for comparing a value of a given homogeneous coordinate of a vertex position of a polygon relative to a plurality of clipping planes. The plurality of clipping planes includes both regular and guard band clipping planes. The clip testing unit includes registers for receiving and storing a W value corresponding to the vertex position, as well as a coordinate input register for receiving and storing the given homogeneous coordinate. The W value is conveyed to a guard band W generation unit, which generates a guard band W value in response thereto. The clip testing unit also includes a clip compare unit coupled to receive the W value, the guard band W value and the value of the given coordinate. The clip compare unit receives and compares the W value and the value of the given coordinate, generating one or more first clip signals in response thereto.

Abstract: A lighting unit which exhibits improved handling of incoming color values corresponding to a polygon. The lighting unit includes an input buffer for storing a plurality of color values, a mode register including a color mode field specifying whether the plurality of color values corresponds to the front or back side of the polygon. Furthermore, the lighting unit includes a register file for storing color information. The register file includes a first and second plurality of registers for storing front and back side color information, respectively. Still further, the lighting unit includes input/output logic configured to perform a transfer color instruction, which first comprises accessing the mode register to obtain a value of the color mode field, and then transferring the plurality of color values from the input buffer to one or more registers within the register file.

Abstract: A floating point processor for a 3-D graphics accelerator which includes improved performance over prior art designs. The floating point processor includes three specialized engines or function units which streamline floating point operations and which provide improved performance over prior systems. In the preferred embodiment, the floating point processor comprises a floating point core (F-core), a lighting core (L-Core), and a set-up core (S-core). Computations for triangles and vectors are split over the three function units for improved efficiency. The F-core processor receives geometry primitive data and performs floating point operations on the received geometry data. The L-Core processor comprises a fixed point computational unit for performing lighting computations. The set-up core comprises a fixed point computational unit for performing set-up calculations for geometric primitives.

Abstract: A method and apparatus for accurate head-tracked stereo display on a workstation CRT is disclosed that corrects inaccuracies caused by CRT optical properties. The correction includes modification of a viewing matrix equation to adjust the physical coordinates of a display window. An alternative correction models the CRT surface as multiple flat "patches" positioned and titled to approximate the spherical or cylindrical shape of the actual screen, and each patch is rendered separately with a patch-specific viewing matrix. Another alternative correction uses angle of view information obtained directly with eye tracking, or indirectly through a "hot spot" determination to bias correction at the point of viewing.

Abstract: Electronic apparatus comprises a main circuit board, a transition board, and a first connector composed of a first part attached to the main circuit board at one edge thereof and a second part attached to the transition board at a first main face thereof, whereby when the first and second parts are engaged the transition board is substantially perpendicular to the main circuit board. The transition board is attached to a connector board so that the second main face of the transition board is in spaced substantially parallel confronting relationship with a first main face of the connect or board. A second connector is composed of a first part attached to the connector board at its first main face and a second part attached to the transition board at its second main face.

Abstract: A set in structure (SIS) list is established for each DAG structure of a DAG structure network. Additionally, a used before set (UBS) list is established for each structure invoking element in the DAG data structure. At each invocation of a DAG structure, a list of traversal state list (TSL) attribute values that need to saved and subsequently restored (SAR) for the invoking DAG data structure is established. The SAR list of an invoked DAG data structure is established based on a list of attributes needed by the invoking DAG data structure (N) and the SIS of the invoked DAG data structure. The N list is established based on the UBS list of the invoking structure element of the invoking DAG structure, and a need from child (NFC) attribute list of the invoking DAG data structure. Only values of the TSL attributes included in the SAR list are saved before the invoked DAG data structure is traversed.

Abstract: A method and apparatus for generating complex 3D stereo images in response to real time viewer head movement by dynamically accessing pairs of stereo images selected from among a precomputed set of images. The precomputed images correspond to a predetermined set of possible viewpoints, and are accessed based upon a prediction of viewer head movement. The arrangement of predetermined viewpoints may be along one, two, or three dimensions.