Patents by Inventor Michael Dreesen
Michael Dreesen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063795Abstract: An electronic circuit for dynamic evaluation of logic functions includes a discharging circuit, a first keeper circuit, a delay circuit and a second keeper circuit. The discharging circuit is configured to discharge an evaluation node. The first keeper circuit is configured to charge the evaluation node and configured to be disabled responsively to a first keeper control indication. The delay circuit is configured to generate a second keeper control indication that is delayed relative to the first keeper control indication. The second keeper circuit is configured to retain a charge on the evaluation node responsively to the second keeper control indication.Type: ApplicationFiled: February 12, 2023Publication date: February 22, 2024Inventors: Andrew Russell, Michael A. Dreesen, Adam Johnson, Jacek R. Wiatrowski
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Patent number: 11755050Abstract: An adaptive current mirror circuit for current shaping with temperature is disclosed. The adaptive current mirror includes a current generator circuit configured to receive and input current and generate an output current using the input current and an overdrive voltage. The adaptive current mirror further includes a compensation circuit configured to adjust a value of the overdrive voltage based on temperature.Type: GrantFiled: September 7, 2021Date of Patent: September 12, 2023Assignee: Apple Inc.Inventors: Mohammad Kazemi, Michael A. Dreesen
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Patent number: 11688437Abstract: An amplifier system includes a differential amplifier and a calibration circuit. In response to a calibration operation, the calibration circuit generates a calibration value based on a test output signal generated by the differential amplifier circuit using a test input signal. The calibration value may be used to adjust loading of internal nodes of the differential amplifier circuit to compensate for imbalance in the differential amplifier circuit resulting from variation in manufacturing. By compensating for the imbalance, the offset of the differential amplifier may be reduced, allowing resolution of smaller differential voltages, thereby improving the performance of circuits employing the differential amplifier circuit.Type: GrantFiled: September 22, 2021Date of Patent: June 27, 2023Assignee: Apple Inc.Inventors: Michael A. Dreesen, Shawn Searles, Jaemyung Lim, Jacek R. Wiatrowski
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Publication number: 20230074425Abstract: An adaptive current mirror circuit for current shaping with temperature is disclosed. The adaptive current mirror includes a current generator circuit configured to receive and input current and generate an output current using the input current and an overdrive voltage. The adaptive current mirror further includes a compensation circuit configured to adjust a value of the overdrive voltage based on temperature.Type: ApplicationFiled: September 7, 2021Publication date: March 9, 2023Inventors: Mohammad Kazemi, Michael A. Dreesen
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Publication number: 20220101914Abstract: A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.Type: ApplicationFiled: May 11, 2021Publication date: March 31, 2022Inventors: Michael A. Dreesen, Ajay Bhatia, Michael R. Seningen, Greg M. Hess, Siddhesh Gaiki
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Publication number: 20220101892Abstract: An amplifier system includes a differential amplifier and a calibration circuit. In response to a calibration operation, the calibration circuit generates a calibration value based on a test output signal generated by the differential amplifier circuit using a test input signal. The calibration value may be used to adjust loading of internal nodes of the differential amplifier circuit to compensate for imbalance in the differential amplifier circuit resulting from variation in manufacturing. By compensating for the imbalance, the offset of the differential amplifier may be reduced, allowing resolution of smaller differential voltages, thereby improving the performance of circuits employing the differential amplifier circuit.Type: ApplicationFiled: September 22, 2021Publication date: March 31, 2022Inventors: Michael A. Dreesen, Shawn Searles, Jaemyung Lim, Jacek R. Wiatrowski
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Patent number: 10812081Abstract: A computer system may include circuit blocks that may operate in different operating modes. When operating in a retention mode, a voltage level of a local power supply node for a particular circuit block may be less than a voltage level of the local power supply node when the particular circuit block is operating in an active mode. An output buffer circuit may be configured to generate, when the particular circuit block is operating in retention mode, an output signal using a circuit signal generated by the particular circuit block, and a voltage level corresponding to the active mode of operation.Type: GrantFiled: September 27, 2019Date of Patent: October 20, 2020Assignee: Apple Inc.Inventors: Michael R. Seningen, Michael A. Dreesen
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Patent number: 10340900Abstract: In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.Type: GrantFiled: December 22, 2016Date of Patent: July 2, 2019Assignee: Apple Inc.Inventors: Amrinder S. Barn, Bo Zhao, Michael A. Dreesen
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Publication number: 20180181193Abstract: In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.Type: ApplicationFiled: December 22, 2016Publication date: June 28, 2018Inventors: Amrinder S. Barn, Bo Zhao, Michael A. Dreesen
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Patent number: 9792979Abstract: Systems, apparatuses, and methods for tracking a retention voltage are disclosed. In one embodiment, a circuit is utilized for generating a standby voltage for a static random-access memory (SRAM) array. The circuit tracks the leakage current of the bitcells of the SRAM array as the leakage current varies over temperature. The circuit mirrors this leakage current and tracks the higher threshold voltage of a p-channel transistor or an n-channel transistor, with the p-channel and n-channel transistors matching the transistors in the bitcells of the SRAM array. The circuit includes a voltage regulator to supply power to the SRAM array at a supply voltage proportional to the higher threshold voltage tracked. Setting a supply voltage of the SRAM array based on threshold voltages and leakage current may reduce power consumption as compared to using a supply voltage based on a worst case operating conditions assumption for the SRAM array.Type: GrantFiled: November 30, 2016Date of Patent: October 17, 2017Assignee: Apple Inc.Inventor: Michael A. Dreesen
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Patent number: 9529533Abstract: An apparatus for modifying a voltage level of a memory array power supply is disclosed. A first column may include a first plurality of data storage cells coupled to a first local power supply signal and a second column may include a second plurality of data storage cells coupled to a second local power supply signal. A first switch may be configured to selectively coupled the first local power supply signal to either a first power signal or a second power supply signal dependent upon a value of a first selection signal, and a second switch may be configured to selectively couple the second local power supply signal to either the first power supply signal or the second power supply signal dependent upon a value of a second selection signal.Type: GrantFiled: June 9, 2016Date of Patent: December 27, 2016Assignee: Apple Inc.Inventors: Michael A. Dreesen, Naveen Javarappa, Ajay Kumar Bhatia, Greg M. Hess
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Publication number: 20160240266Abstract: Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.Type: ApplicationFiled: February 13, 2015Publication date: August 18, 2016Inventors: Michael R. Seningen, Michael A. Dreesen, Edward M. McCombs
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Patent number: 9411392Abstract: A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality of sub-arrays and sense amplifiers. Each of the sub-arrays may include a plurality of memory cells. Each of the sense amplifiers may be coupled to a respective one of the plurality of sub-arrays and may read data stored in a first memory cell included in the respective sub-array. The system may also include one or more write driver circuits. A first write driver circuit may be coupled to at least two of the plurality of sub-arrays. The first write driver circuit may be configured to store data into a second memory cell in one of the at least two sub-arrays.Type: GrantFiled: June 4, 2014Date of Patent: August 9, 2016Assignee: Apple Inc.Inventors: Ajay Bhatia, Michael Dreesen
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Patent number: 9412469Abstract: Methods and apparatuses for performing a disturb test on a memory are disclosed. Circuitry may be configured to store test data into one or more data storage cells. A regulation circuit may adjust a level of a power supply coupled to the one or more data storage cells from a first level to a second level. Once the voltage level of the power supply has reached the second level, the circuitry may perform a read operation on the one or more data storage cells. Upon completion of the read operation, the regulation circuit may return the voltage level of the power supply to the first level, and the circuitry may perform another read operation, the results of which, the circuitry may compare to the test data.Type: GrantFiled: February 13, 2015Date of Patent: August 9, 2016Assignee: Apple Inc.Inventors: Michael R. Seningen, Michael A. Dreesen, Edward M. McCombs
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Patent number: 9411391Abstract: A system and method for managing power in a memory, wherein the system may include a processor and a memory unit coupled to the processor. The memory unit may initialize an address decoder into a first power mode. In response to receiving a command and an address corresponding to a location within the memory unit, the memory unit may use the first stage of the address decoder to decode at least a portion of the address. The memory unit may further switch a selected portion of a second stage of the address decoder from the first power mode to the second power mode, wherein the selected portion of the second stage of the address decoder is selected dependent upon an output signal of the first stage of the address decoder.Type: GrantFiled: May 5, 2014Date of Patent: August 9, 2016Assignee: Apple Inc.Inventors: Ajay Bhatia, Michael Dreesen
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Patent number: 9189052Abstract: A system, a voltage regulator and a method for regulating power are disclosed, wherein the system may include a processor, a voltage regulator circuit, and a memory unit. The voltage regulator circuit may be configured to generate a first power supply voltage provided to the memory unit. The voltage regulator circuit may be further configured to adjust a voltage level of two output nodes dependent upon a level of the first power supply voltage and a level of a reference voltage. The voltage regulator circuit may be further configured to adjust the level of the first power supply signal dependent upon the level of at least one of the two output voltages. The voltage regulating circuit may also provide the first output voltage to the second output voltage via an impedance.Type: GrantFiled: June 4, 2014Date of Patent: November 17, 2015Assignee: Apple Inc.Inventors: Ajay Bhatia, Michael Dreesen
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Publication number: 20150227456Abstract: A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality of sub-arrays and sense amplifiers. Each of the sub-arrays may include a plurality of memory cells. Each of the sense amplifiers may be coupled to a respective one of the plurality of sub-arrays and may read data stored in a first memory cell included in the respective sub-array. The system may also include one or more write driver circuits. A first write driver circuit may be coupled to at least two of the plurality of sub-arrays. The first write driver circuit may be configured to store data into a second memory cell in one of the at least two sub-arrays.Type: ApplicationFiled: June 4, 2014Publication date: August 13, 2015Inventors: Ajay Bhatia, Michael Dreesen
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Publication number: 20150228312Abstract: A system, a voltage regulator and a method for regulating power are disclosed, wherein the system may include a processor, a voltage regulator circuit, and a memory unit. The voltage regulator circuit may be configured to generate a first power supply voltage provided to the memory unit. The voltage regulator circuit may be further configured to adjust a voltage level of two output nodes dependent upon a level of the first power supply voltage and a level of a reference voltage. The voltage regulator circuit may be further configured to adjust the level of the first power supply signal dependent upon the level of at least one of the two output voltages. The voltage regulating circuit may also provide the first output voltage to the second output voltage via an impedance.Type: ApplicationFiled: June 4, 2014Publication date: August 13, 2015Inventors: Ajay Bhatia, Michael Dreesen
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Publication number: 20150227186Abstract: A system and method for managing power in a memory, wherein the system may include a processor and a memory unit coupled to the processor. The memory unit may initialize an address decoder into a first power mode. In response to receiving a command and an address corresponding to a location within the memory unit, the memory unit may use the first stage of the address decoder to decode at least a portion of the address. The memory unit may further switch a selected portion of a second stage of the address decoder from the first power mode to the second power mode, wherein the selected portion of the second stage of the address decoder is selected dependent upon an output signal of the first stage of the address decoder.Type: ApplicationFiled: May 5, 2014Publication date: August 13, 2015Applicant: Apple Inc.Inventors: Ajay Bhatia, Michael Dreesen
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Patent number: 8947967Abstract: Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.Type: GrantFiled: December 21, 2012Date of Patent: February 3, 2015Assignee: Advanced Micro Devices Inc.Inventors: Michael Dreesen, Stephen Greenwood, Bruce Doyle