Patents by Inventor Michael E. Connell

Michael E. Connell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7727785
    Abstract: A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to an opposite side from a stress-causing layer before the semiconductor die or wafer is significantly warped are provided. The SBL may also serve as, or support, an adhesive layer for die attach and be of a markable material for an enhanced marking method.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: June 1, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Michael E. Connell, Tongbi Jiang
  • Patent number: 7297412
    Abstract: Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of microelectronic components in a batch fashion. In one embodiment, an adhesive payer is applied on a rear surface of a wafer. A plurality of spaced-apart adhesive pads are defined within the adhesive layer. Each adhesive pad may cover less than the entire back surface area of the component to which it is attached. A mounting member (e.g., dicing tape) may be attached to the adhesive layer and, in some embodiments, the adhesive layer may be treated so that the mounting member is less adherent to the adhesive pads than to other parts of the adhesive layer, easing removal of the adhesive pads with the microelectronic components.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: November 20, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Michael E. Connell, Tongbi Jiang
  • Patent number: 7169685
    Abstract: A method for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped are provided. The SBL may also serve as, or support, an adhesive layer for die attach, and be of a markable material for an enhance marking method.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: January 30, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Michael E. Connell, Tongbi Jiang
  • Patent number: 7037751
    Abstract: Manufacture of stacked microelectronic devices is facilitated by producing subassemblies wherein adhesive pads are applied to the back surfaces of a plurality of microelectronic components in a batch fashion. In one embodiment, an adhesive payer is applied on a rear surface of a wafer. A plurality of spaced-apart adhesive pads are defined within the adhesive layer. Each adhesive pad may cover less than the entire back surface area of the component to which it is attached. A mounting member (e.g., dicing tape) may be attached to the adhesive layer and, in some embodiments, the adhesive layer may be treated so that the mounting member is less adherent to the adhesive pads than to other parts of the adhesive layer, easing removal of the adhesive pads with the microelectronic components.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: May 2, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Michael E. Connell, Tongbi Jiang
  • Patent number: 6894380
    Abstract: A method of packaging semiconductor devices is described. In one embodiment, the method comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: May 17, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Michael E. Connell
  • Patent number: 6882036
    Abstract: Methods and apparatuses for forming thin microelectronic dies. A method in accordance with one embodiment of the invention includes releasably attaching a microelectronic substrate to a support member with an attachment device. The microelectronic substrate can have a first surface, a second surface facing opposite from the first surface, and a first thickness between the first and second surfaces. The attachment device can have a releasable bond with the microelectronic substrate, wherein the bond has a bond strength that is reduced upon exposure to at least one energy. The support member can be at least partially transmissive to the at least one energy. The method can further include reducing a thickness of the microelectronic substrate and directing a quantity of the at least one energy through the support member to the attachment device to reduce the strength of the bond between the attachment device and the microelectronic substrate.
    Type: Grant
    Filed: April 29, 2004
    Date of Patent: April 19, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Nathan R. Draney, Michael E. Connell
  • Publication number: 20040203188
    Abstract: Methods and apparatuses for forming thin microelectronic dies. A method in accordance with one embodiment of the invention includes releasably attaching a microelectronic substrate to a support member with an attachment device. The microelectronic substrate can have a first surface, a second surface facing opposite from the first surface, and a first thickness between the first and second surfaces. The attachment device can have a releasable bond with the microelectronic substrate, wherein the bond has a bond strength that is reduced upon exposure to at least one energy. The support member can be at least partially transmissive to the at least one energy. The method can further include reducing a thickness of the microelectronic substrate and directing a quantity of the at least one energy through the support member to the attachment device to reduce the strength of the bond between the attachment device and the microelectronic substrate.
    Type: Application
    Filed: April 29, 2004
    Publication date: October 14, 2004
    Inventors: Nathan R. Draney, Michael E. Connell
  • Patent number: 6762074
    Abstract: Methods and apparatuses for forming thin microelectronic dies. A method in accordance with one embodiment of the invention includes releasably attaching a microelectronic substrate to a support member with an attachment device. The microelectronic substrate can have a first surface, a second surface facing opposite from the first surface, and a first thickness between the first and second surfaces. The attachment device can have a releasable bond with the microelectronic substrate, wherein the bond has a bond strength that is reduced upon exposure to at least one energy. The support member can be at least partially transmissive to the at least one energy. The method can further include reducing a thickness of the microelectronic substrate and directing a quantity of the at least one energy through the support member to the attachment device to reduce the strength of the bond between the attachment device and the microelectronic substrate.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: July 13, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Nathan R. Draney, Michael E. Connell
  • Publication number: 20040104491
    Abstract: A method and apparatus for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped. The SBL may also serve as, or support, an adhesive layer for die attach and be of a markable material for an enhanced marking method.
    Type: Application
    Filed: November 12, 2003
    Publication date: June 3, 2004
    Inventors: Michael E. Connell, Tongbi Jiang
  • Publication number: 20030162368
    Abstract: A method and apparatus for balancing layer-caused compressive or tensile stress in a semiconductor die, die wafer or similar substrate uses a stress-balancing layer (SBL) attached to the opposite side from the stress-causing layer before the die or wafer is significantly warped. The SBL may also serve as, or support, an adhesive layer for die attach, and be of a markable material for an enhanced marking method.
    Type: Application
    Filed: February 25, 2002
    Publication date: August 28, 2003
    Inventors: Michael E. Connell, Tongbi Jiang
  • Publication number: 20030067083
    Abstract: A method of packaging semiconductor devices is described. In one embodiment, the method comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto.
    Type: Application
    Filed: August 28, 2002
    Publication date: April 10, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Michael E. Connell
  • Patent number: 6514795
    Abstract: A method of packaging semiconductor devices is described. In one embodiment, the method comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: February 4, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Michael E. Connell
  • Patent number: 6198861
    Abstract: A method of analyzing a chemical reaction in a material including the steps of embedding in a material an optical fiber having a cladding along substantially the entire length thereof that is in contact with the material, transmitting light through the optical fiber, and performing evanescent wave spectroscopy on the light transmitted through the optical fiber. The optical fiber preferably has a core 10-30 &mgr;m in diameter and a cladding that is on the order of 1 &mgr;m thick.
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: March 6, 2001
    Assignee: South Dakota School of Mines and Technology
    Inventors: Jon J. Kellar, William M. Cross, Farrah J. Johnson, Michael E. Connell