Abstract: A gas distribution head for plasma deposition and etch systems includes an electrically conductive casing surrounding a plenum chamber. The casing includes a gas inlet and a gas outlet in the form of apertures through the casing. An electrically conductive electrode is positioned within the casing with respect to the interior surfaces of the casing such that a plasma forms between the electrode and the casing upon application of an electrical potential between them. A reactive gas is injected between the two electrodes which is struck to form a plasma for cleaning the inner surfaces of the plasma chamber of undesirable particulates and residues.

Abstract: In a method of bonding a pad on a semiconductor chip to a corresponding pad on a carrier, a wire ball is attached to the pad on the chip by bonding one end of a low melting temperature aluminum alloy bond wire to the chip pad. The wire is then broken off at the bond. A bead is formed on the chip pad by heating the ball to a temperature slightly above the melting point of the bond wire material for a predetermined period of time. The melted bead is then placed into contact with a corresponding pad on the carrier.

Abstract: An optical interconnect structure, formed on a substrate, includes optical interconnects each of which includes a core member constructed of a material having a first predetermined index of refraction. A cladding layer surrounds each core member. The cladding layer is formed of a material having a second predetermined index of refraction, the magnitude of which is less than the first predetermined index of refraction. At least one optical port exposes at least a portion of the core member of at least one optical interconnect. The optical port may be located on a top portion of an optical interconnect or at one or both ends of an optical interconnect.

Abstract: An optical interconnect structure, formed on a substrate, optically interconnects optoelectronic transmitting and receiving devices. The optical interconnect structure includes optical interconnects each of which includes a core member constructed of a material having a first predetermined index of refraction. The ends of the core members are chemically bonded either to an optoelectronic device or a core member of another optical interconnect. A cladding layer surrounds each core member. Each end of a cladding layer proximate to an optoelectronic device is chemically bonded to that device. The cladding layer is formed of a material having a second predetermined index of refraction, the magnitude of which is less than the magnitude of the first predetermined index of refraction.

Abstract: A pad for planarization by mechanical polishing of a dielectric layer formed over features on a wafer in the manufacture of semiconductor devices has a substantially planar polishing face. The pad includes a soft matrix material and a substance for stiffening distributed in the pad so as to effect stiffening of the pad. The substance for stiffening is composed of a hard substance, which in a preferred embodiment is in the form of discrete particles distributed substantially uniformly throughout substantially all of the pad.

Abstract: A carrier for a semiconductor wafer or other substrate has an outer portion adapted for engagement by equipment for processing wafers. Interior to the outer portion a substantially planar supporting surface is provided. A retaining lip is provided above the plane in which the supporting surface lies by at least the height of a wafer of a selected size. The circumference of the retaining lip is of sufficient size and proper shape to permit the passage of a wafer of the selected size. The carrier is undercut under the lip, whereby a wafer of the selected size, when placed on the supporting surface, may be retained.In one embodiment, the carrier has a cylindrical shape. The top of the carrier includes a flat outer ring-like surface. The supporting surface and the circumference of the retaining lip are both circular.

Abstract: An integrated circuit electronic grid device includes first and second metal layers wherein a layer of a dielectric medium is disposed between the metal layers. A third metal layer is disposed above the second metal layer and insulated from the second metal layer by another layer of a dielectric medium. The first and second metal layers are biased with respect to each other to cause a flow electrons from the first metal layer toward the second metal layer. The second metal layer is provided with a large plurality of holes adapted for permitting the flow of electrons to substantially pass therethrough and to travel toward the third metal layer. A fourth metal layer is disposed above the third metal layer to collect the electrons wherein the third metal layer is also provided with a large plurality of holes to permit the electrons to flow therethrough and continue toward the fourth metal layer.

Abstract: A suitable inert thermal gas such as argon is introduced onto the backside of wafers being processed in a CVD reactor during the deposition of tungsten or other metals and silicides, to avoid deposition of material on the backside of the wafers being processed. Each process station includes a gas dispersion head disposed over a platen. The platen has a circular depresssion for receiving a wafer, and an annular groove provided in the floor of the depression, near the wall thereof. Heated and pressurized backside gas is introduced into the groove so that the wafer is maintained in a position above the floor of the depression but still within it. In this manner, backside gas vents from beneath the edge of the wafer on the platen and prevents the process gases from contacting the wafer in a transfer region above the platen, so that the wafer can be transported to or from the platen with a suitable wafer transfer mechanism.

Abstract: An optical interconnect structure, formed on a substrate, optically interconnects optoelectronic transmitting and receiving devices. The optical interconnect structure includes optical interconnects each of which includes a core member constructed of a material having a first predetermined index of refraction. The ends of the core members are chemically bonded either to an optoelectronic device or a core member of another optical interconnect. A cladding layer surrounds each core member. Each end of a cladding layer proximate to an optoelectronic device is chemically bonded to that device. The cladding layer is formed of a material having a second predetermined index of refraction, the magnitude of which is less than the magnitude of the first predetermined index of refraction.

Abstract: A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.

Abstract: A thin film capacitor for use in an integrated circuit includes a lower plate disposed on the silicon substrate of the integrated circuit. The lower plate comprises a barrier layer of conductive material which prevents transport of silicon from the silicon substrate into a layer of dielectric material which is disposed between the lower plate and an upper plate. A portion of the barrier layer can be consumed and transferred into dielectric material by, for example, high temperature oxidation which generates a symmetric series capacitor with the dielectric layer. A layer comprising an oxide of the barrier layer material is formed between the barrier layer and the dielectric layer by consuming an upper portion of the barrier layer.

Abstract: The surface of a semiconductor wafer is planarized by disposing the wafer in a wafer plane and rotating the wafer within the wafer plane wherein the rotation is around an axis perpendicular to the plane. A stream of particles is transported to the surface of the wafer while the wafer is rotating wherein the angle between the stream of particles and the wafer plane is small. The stream of particles mills the surface of the wafer thereby planarizing the surface of the wafer. The angle between the stream of particles and the wafer plane is preferably less than thirty degrees. The particles may be argon ions and may be chemically active particles or physical particles.

Abstract: Vertically propagated defects in integrated circuits are detected utilizing an apparatus which includes a first meander structure formed on or in a substrate and a second meander structure electrically insulated from the first meander. Each meander includes intermediate segments, the ends of which are interconnected by folded segments. A first set metal of strips are electrically insulated from the first and second meanders. The ends of each strip in the first set are electrically connected to the ends of a corresponding intermediate segment of the first meander. A second set metal or strips are electrically insulated from the first set of strips, the first meander and the second meander. The ends of each strip in the second set are electrically connected to the ends of a corresponding intermediate segment of the second meander and at least a portion of the second set of strips overlies at least a portion of the first set of strips.

Abstract: A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.

Abstract: A semiconductor integrated circuit device includes a high performance interconnect structure which comprises a plurality of interconnects, with each interconnect being structurally separated from the remaining interconnects except at electrical contact points. In one embodiment, each interconnect is substantially surrounded by a layer of dielectric material, there being gaps between each adjacent layer of surrounding dielectric material. Another embodiment, a layer of electrically conductive material is formed over the surrounding dielectric layer preferably filling in the gaps between adjacent layers of surrounding dielectric material. The layer of electrically conductive material acts as a ground plane and heat sink.

Abstract: A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with silicon and compounds thereof, and which remain stable at temperatures exceeding approximately 500.degree. C.

Abstract: A holder for milling a countersink filler plug, the holder having a bolt-like configured support on which the filler plug is mounted prior to the milling procedure. A sleeve slidably circumscribes the bolt-like support and is of a height less than the height of the bolt-like support. Adjustment washers are positioned adjacent the sleeve in order to regulate the position of the sleeve relative to the bolt-like support. The filler plug rests upon the sleeve circumscribing a portion of the bolt-like support such that the porton of the filler plug which is not in abutment with the bolt-like support can be easily removed by the milling tool during the milling procedure.

Abstract: Spot defects are detected utilizing an apparatus which comprises a meander structure formed in a high resistivity material on a substrate. The meandor includes intermediate segments, the ends of which are interconnected by folded segments such that an electrical circuit having electrical resistance R is formed between the ends of the meander. A strip of high electrical conductivity material is formed in substantial alignment with and is electrically insulated from a corresponding one of each of the intermediate segments. Each end of each strip is electrically connected to a corresponding end of a corresponding intermediate segment. Defects are identified by measuring the resistance R, between the ends of the meander. This measured value is then compared to the calculated value of R. If the value of the measured resistance is substantially smaller than the calculated value, a flaw due to a spot of additional high conductivity material, is considered to be present.

Abstract: A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride layer between the doped silicon substrate and the refractory metal silicide conductive layer. Dopant out-diffusion is further retarded, and contact resistance lowered, by adding a thin layer of refractory metal between the refractory metal nitride layer and the silicon substrate.

Abstract: In a process of forming vias for multilevel interconnects used in integrated circuits, a layer of a first metal is formed on a semiconductor substrate. A layer of a second metal is formed on the first metal layer. The second metal layer is etched in a predetermined via pattern with a second etchant which reacts with the second metal and which is substantially unreactive with the first metal. The first metal layer is then etched with a first etchant which reacts with the first metal and which is substantialy unreactive with the second metal or with the semiconductor substrate in order to form a predetermined contacting relationship with the predetermined via pattern. This process may be used to generate second and subsequent levels of vias and interconnects which can be used to contact metal layer at any level directly to the substrate by building via posts from the substrate to any desired metal layer.