Patents by Inventor Michael F. Keaveney
Michael F. Keaveney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11539353Abstract: Rotary traveling wave oscillator-based (RTWO-based) frequency multipliers are provided herein. In certain embodiments, an RTWO-based frequency multiplier includes an RTWO that generates a plurality of clock signal phases of a first frequency, and an edge combiner that processes the clock signal phases to generate an output clock signal having a second frequency that is a multiple of the first frequency. The edge combiner can be implemented as a logic-based combining circuit that combines the clock signal phases from the RTWO. For example, the edge combiner can include parallel stacks of transistors operating on different clock signal phases, with the stacks selectively activating based on timing of the clock signal phases to generate the output clock signal of multiplied frequency.Type: GrantFiled: July 22, 2021Date of Patent: December 27, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Mohamed A. Shehata, James Breslin, Michael F. Keaveney, Hyman Shanan
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Patent number: 11527992Abstract: Rotary traveling wave oscillators (RTWOs) with distributed stubs are provided. In certain embodiments, an RTWO includes segments that are implemented using distributed stubs to mitigate flicker noise upconversion arising from transmission line dispersion. For example, a distance between the distributed stubs can be selected to intentionally generate a phase difference between transmission line modes, thereby cancelling out phase shifts due to transmission line dispersion. In particular, each segment is subdivided into multiple transmission line sections with a maintaining amplifier electrically connected to one of the sections and a tuning capacitor array connected to adjacent transmission line sections.Type: GrantFiled: July 22, 2020Date of Patent: December 13, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Mohamed A. Shehata, Michael F. Keaveney
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Publication number: 20220247396Abstract: Rotary traveling wave oscillator-based (RTWO-based) frequency multipliers are provided herein. In certain embodiments, an RTWO-based frequency multiplier includes an RTWO that generates a plurality of clock signal phases of a first frequency, and an edge combiner that processes the clock signal phases to generate an output clock signal having a second frequency that is a multiple of the first frequency. The edge combiner can be implemented as a logic-based combining circuit that combines the clock signal phases from the RTWO. For example, the edge combiner can include parallel stacks of transistors operating on different clock signal phases, with the stacks selectively activating based on timing of the clock signal phases to generate the output clock signal of multiplied frequency.Type: ApplicationFiled: July 22, 2021Publication date: August 4, 2022Inventors: Mohamed A. Shehata, James Breslin, Michael F. Keaveney, Hyman Shanan
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Publication number: 20210091721Abstract: Rotary traveling wave oscillators (RTWOs) with distributed stubs are provided. In certain embodiments, an RTWO includes segments that are implemented using distributed stubs to mitigate flicker noise upconversion arising from transmission line dispersion. For example, a distance between the distributed stubs can be selected to intentionally generate a phase difference between transmission line modes, thereby cancelling out phase shifts due to transmission line dispersion. In particular, each segment is subdivided into multiple transmission line sections with a maintaining amplifier electrically connected to one of the sections and a tuning capacitor array connected to adjacent transmission line sections.Type: ApplicationFiled: July 22, 2020Publication date: March 25, 2021Inventors: Mohamed A. Shehata, Michael F. Keaveney
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Publication number: 20180331712Abstract: Aspects of this disclosure relate to active antenna calibration. In some embodiments, a local oscillator signal can be injected into the receive path for misalignment measurement and calibration of the receive path, a transmit signal from a transmit path can be coupled to a receive path, and the transmit path can be calibrated relative to the receive path.Type: ApplicationFiled: May 9, 2017Publication date: November 15, 2018Inventors: Michael W. O'Brien, Michael F. Keaveney, Emil Ivanov Entchev, James Breslin
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Patent number: 10128894Abstract: Aspects of this disclosure relate to active antenna calibration. In some embodiments, a local oscillator signal can be injected into the receive path for misalignment measurement and calibration of the receive path, a transmit signal from a transmit path can be coupled to a receive path, and the transmit path can be calibrated relative to the receive path.Type: GrantFiled: May 9, 2017Date of Patent: November 13, 2018Assignee: ANALOG DEVICES GLOBALInventors: Michael W. O'Brien, Michael F. Keaveney, Emil Ivanov Entchev, James Breslin
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Patent number: 9503109Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.Type: GrantFiled: June 1, 2015Date of Patent: November 22, 2016Assignee: ANALOG DEVICES GLOBALInventors: David J. McLaurin, Christopher W. Angell, Michael F. Keaveney
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Patent number: 9484935Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.Type: GrantFiled: December 19, 2013Date of Patent: November 1, 2016Assignee: Analog Devices GlobalInventors: Hyman Shanan, Michael F. Keaveney
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Patent number: 9413309Abstract: Provided herein are apparatus and methods for a cascode amplifier topology for millimeter-wave power application. The cascode amplifier can use a neutralized common source stage cascoded with a bootstrapped common gate stage to provide an amplifier topology having enhanced performance, gain, stability and reliability. Additionally, a bootstrap capacitor of the common gate stage can be patterned between the source fingers and the drain fingers of a cascode transistor so as to improve device performance. Operating as an RF power amplifier, a single-stage cascode amplifier using the neutralized common source stage with the bootstrapped common gate stage can provide greater than 15 dB of power gain to signals of the E band.Type: GrantFiled: March 25, 2015Date of Patent: August 9, 2016Assignee: ANALOG DEVICES GLOBALInventors: Dixian Zhao, Patrick Reynaert, Michael F. Keaveney
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Patent number: 9413366Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO and a calibration voltage generation circuit that can generate a calibration voltage for controlling a tuning voltage input of the VCO when the VCO is being coarsely tuned. Additionally, the calibration voltage generation circuit can sense a temperature of the PLL, and can control a voltage level of the calibration voltage to provide compensation based on the sensed temperature. The calibration voltage generation circuit can include a bandgap reference circuit configured to generate a zero-to-absolute-temperature (ZTAT) current and a proportional-to-absolute temperature (PTAT) current, and the calibration voltage can be generated based in part on a difference between the PTAT current and the ZTAT current.Type: GrantFiled: December 19, 2013Date of Patent: August 9, 2016Assignee: ANALOG DEVICES GLOBALInventors: Hyman Shanan, Michael F. Keaveney
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Publication number: 20150263742Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.Type: ApplicationFiled: June 1, 2015Publication date: September 17, 2015Inventors: David J. McLaurin, Christopher W. Angell, Michael F. Keaveney
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Publication number: 20150180486Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO and a calibration voltage generation circuit that can generate a calibration voltage for controlling a tuning voltage input of the VCO when the VCO is being coarsely tuned. Additionally, the calibration voltage generation circuit can sense a temperature of the PLL, and can control a voltage level of the calibration voltage to provide compensation based on the sensed temperature. The calibration voltage generation circuit can include a bandgap reference circuit configured to generate a zero-to-absolute-temperature (ZTAT) current and a proportional-to-absolute temperature (PTAT) current, and the calibration voltage can be generated based in part on a difference between the PTAT current and the ZTAT current.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Applicant: Analog Devices TechnologyInventors: Hyman Shanan, Michael F. Keaveney
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Publication number: 20150180485Abstract: Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Applicant: Analog Devices TechnologyInventors: Hyman Shanan, Michael F. Keaveney
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Patent number: 9048847Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.Type: GrantFiled: September 24, 2013Date of Patent: June 2, 2015Assignee: ANALOG DEVICES GLOBALInventors: David J McLaurin, Christopher W Angell, Michael F Keaveney
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Publication number: 20150084676Abstract: Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.Type: ApplicationFiled: September 24, 2013Publication date: March 26, 2015Applicant: Analog Devices TechnologyInventors: David J. McLaurin, Christopher W. Angell, Michael F. Keaveney
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Patent number: 8970310Abstract: As provided herein, in some embodiments, monolithic oscillators with low phase noise, large swing voltages, wide tuning, and high frequency characteristics are obtained by a monolithic integrated circuit having an oscillator core configured to generate a first output signal, and one or more tuning units operatively coupled to the oscillator core. In some embodiments, the oscillator core is a push-push oscillator core having a bipolar junction transistor, and each of the tuning units uses a FET transistor to present a selectable capacitance. In some embodiments, the tuning units have high-voltage and high-frequency capabilities. In some embodiments, the tuning units use MEMS switches to selectively connect capacitances to the oscillator core. In some embodiments, the oscillator core generates a second signal that has twice the frequency of the first frequency.Type: GrantFiled: October 10, 2012Date of Patent: March 3, 2015Assignee: Analog Devices, Inc.Inventors: James Breslin, Michael F. Keaveney
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Publication number: 20140097910Abstract: As provided herein, in some embodiments, monolithic oscillators with low phase noise, large swing voltages, wide tuning, and high frequency characteristics are obtained by a monolithic integrated circuit having an oscillator core configured to generate a first output signal, and one or more tuning units operatively coupled to the oscillator core. In some embodiments, the oscillator core is a push-push oscillator core having a bipolar junction transistor, and each of the tuning units uses a FET transistor to present a selectable capacitance. In some embodiments, the tuning units have high-voltage and high-frequency capabilities. In some embodiments, the tuning units use MEMS switches to selectively connect capacitances to the oscillator core. In some embodiments, the oscillator core generates a second signal that has twice the frequency of the first frequency.Type: ApplicationFiled: October 10, 2012Publication date: April 10, 2014Applicant: Analog Devices, Inc.Inventors: James Breslin, Michael F. Keaveney
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Patent number: 7463710Abstract: A fractional-N synthesizer with programmable output phase including a phase locked loop having an output signal whose frequency is a fractional multiple of an input reference signal, the phase locked loop including a frequency divider. A synchronization circuit responsive to the input reference signal for generating synchronization pulses at integer multiples of M periods of the input reference signal. An interpolator is responsive to F and M, where F is the fractional value and M is the modulus, to provide to the frequency divider an output which is a fractional value equal to, on average, the input fraction. A phase adjustment circuit is responsive to the synchronization circuit for varying the phase of the output signal with respect to the input reference signal.Type: GrantFiled: April 16, 2004Date of Patent: December 9, 2008Assignee: Analog Devices, Inc.Inventors: Patrick Walsh, Michael F. Keaveney
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Patent number: 7317360Abstract: A fractional-N synthesizer system including a plurality of fractional-N synthesizers all updated to simultaneously generate an output frequency from the same reference frequency, a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency; the phase locked loop including a frequency divider, an interpolator responsive to an input fraction to provide to the frequency divider an output which has a fractional value equal to on average, the input fraction; and a timeout circuit responsive to the reference frequency for generating an output a predetermined time after updating to initialize the interpolator in each synthesizer to the same start conditions for locking together the phase of the frequency outputs of all of the synthesizers at the updated frequency.Type: GrantFiled: April 20, 2006Date of Patent: January 8, 2008Assignee: Analog Devices, Inc.Inventor: Michael F. Keaveney
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Patent number: 7202717Abstract: A chopped charge pump with matching up and down pulses including a first pair of current sources, a second pair of current sources, and a switching circuit for switching on in a first phase one current source of each pair to provide up current pulses, and the other current source of each pair to provide down current pulses, and switching on in a second phase the other current source of each pair to provide up current pulses, and the one current source of each pair to provide down current pulses to offset error in the current response of the pairs of current sources.Type: GrantFiled: June 23, 2004Date of Patent: April 10, 2007Assignee: Analog Devices, Inc.Inventors: Michael F. Keaveney, William Hunt