Abstract: A half-bridge includes a first switching device for connecting a terminal to a first potential, and a second switching device for connecting the terminal to a second potential. A method according to the present invention for controlling the half-bridge includes the steps of outputting a closing signal for the first switching device while the second switching device is open, and of ascertaining a latency period between the start of the closing signal and a collapse of a voltage applied across the first switching device. Subsequently, a dead time that lies between an opening of the second switching device and a closing of the first switching device is minimized on the basis of the ascertained latency period.

Abstract: A controller for an electric motor includes a protective circuit for limiting current or for polarity reversal protection, the protective circuit including a field effect transistor having a gate. The protective circuit further includes a control unit for providing a control voltage for the gate, a smoothing capacitor for charge storage being provided at the gate.

Abstract: The invention relates to a device (100) for driving an electromechanical component (200), having: an integrated circuit (10) for driving a semiconductor element having an H-bridge driver apparatus (20); and an interface apparatus (30), by means of which the H-bridge driver apparatus (20) can be used for the electromechanical component (200), wherein, by means of the interface apparatus (30), a temporal operating behavior of a semiconductor component for the integrated circuit (10) can be simulated.

Abstract: The invention relates to a power output stage (1), in particular for a controller of an electrical machine (2) for a motor vehicle, comprising at least one control unit (8) and comprising at least four semiconductor switches (HS1, HS2, LS1, LS2) which can be individually actuated by the control unit (8) and which are connected to at least two half-bridges (4, 5) for operating the electrical machine (2) in order to form a bridge circuit (3), and are connected to a supply line (6) and an earth line (7) of the power output stage (1).

Abstract: A controller for an electric motor includes a protective circuit for limiting current or for polarity reversal protection, the protective circuit including a field effect transistor having a gate. The protective circuit further includes a control unit for providing a control voltage for the gate, a smoothing capacitor for charge storage being provided at the gate.

Abstract: A half-bridge includes a first switching device for connecting a terminal to a first potential, and a second switching device for connecting the terminal to a second potential. A method according to the present invention for controlling the half-bridge includes the steps of outputting a closing signal for the first switching device while the second switching device is open, and of ascertaining a latency period between the start of the closing signal and a collapse of a voltage applied across the first switching device. Subsequently, a dead time that lies between an opening of the second switching device and a closing of the first switching device is minimized on the basis of the ascertained latency period.

Abstract: The invention relates to a power output stage (1), in particular for a controller of an electrical machine (2) for a motor vehicle, comprising at least one control unit (8) and comprising at least four semiconductor switches (HS1, HS2, LS1, LS2) which can be individually actuated by the control unit (8) and which are connected to at least two half-bridges (4, 5) for operating the electrical machine (2) in order to form a bridge circuit (3), and are connected to a supply line (6) and an earth line (7) of the power output stage (1).

Abstract: A method for a control device comprising a processing device, an I/O module and a clock generator for providing a system clock, wherein the processing device and the I/O module are designed to operate with the system clock of the clock generator, comprises the steps of determining that capacity utilization of the processing device is exceeding a predetermined threshold, of determining that the I/O module is in a state in which a change in the system clock is uncritical, and of changing the system clock in order to match the performance capacity of the processing device to the capacity utilization.