Abstract: An indirect variable frequency synthesiser for synthesising selectable frequencies from a reference frequency including a multi-divisor programmable frequency divider located in a feedback loop of the frequency synthesiser for dividing the feedback frequency in the feedback loop, the divider being responsive to a varying control signal applied thereto representative of a rational number of selectable value for selecting the divisor thereof for fractional division of the feedback frequency. A variable modulus interpolator converts a fractional part of the rational number of selectable value to a varying digital code representative of the fractional part of the rational number.

Abstract: A variable modulus interpolator (1) for interpolating a fractional part F M of a rational number by which a reference frequency is to be divided in a multi-divisor divider in a variable frequency synthesizer comprises a third order sigma-delta modulator (3) of MASH cascade configuration having first, second and third sigma-delta stages (5,6,7). The numerator F of the fraction is selectable and is inputted to a first register (10) for inputting to the input of the first sigma-delta stage (5) of the sigma-delta modulator (3). The denominator M of the fraction is selectable and is inputted to a second register 11. A single bit output quantiser (16) in each sigma-delta stage (5,6,7) outputs a sign bit indicative of the sign of the output from an integrator (15) in the corresponding sigma-delta stage (5,6,7).

Abstract: A variable modulus interpolator (1) for interpolating a fractional part F/M of a rational number by which a reference frequency is to be divided in a multi-divisor divider in a variable frequency synthesiser comprises a third order sigma-delta modulator (3) of MASH cascade configuration having first, second and third sigma-delta stages (5,6,7). The numerator F of the fraction is selectable and is inputted to a first register (10) for inputting to the input of the first sigma-delta stage (5) of the sigma-delta modulator (3). The denominator M of the fraction is selectable and is inputted to a second register 11. A single bit output quantiser (16) in each sigma-delta stage (5,6,7) outputs a sign bit indicative of the sign of the output from an integrator (15) in the corresponding sigma-delta stage (5,6,7).