Abstract: A method of providing a clock signal for an embodiment includes performing a calibration for a closed loop control system to determine a control signal value that provides a desired tuning of the closed loop control system. The control signal value is stored and provided to a delay circuit, wherein a delay range and a delay step size of the delay circuit is based on the control signal value. A delay select control signal is provided to the delay circuit to select a specific delay within the delay range.

Abstract: In one example, a method of tuning an oscillator of a phase-locked loop (PLL) circuit includes adjusting a coarse control signal to select one of a plurality of frequency tuning curves of the oscillator. The method includes adjusting a fine control signal to select a position on the selected frequency tuning curve. A frequency of the oscillator is determined by the coarse control signal and the fine control signal. The method includes attempting to detect a lock between a feedback signal and a reference signal. A frequency of the feedback signal is determined by the frequency of the oscillator. The method includes comparing the fine control signal to a reference value if the lock is detected. The method includes adjusting the coarse control signal to select a different one of the frequency tuning curves if the selected position on the selected frequency tuning curve is outside a desired tuning range.

Abstract: In one embodiment, a method is provided for measuring a dynamic phase offset between a PLL's input clock and the PLL's feedback input clock, wherein the input clock is spread spectrum modulated in a spread spectrum mode and is not modulated in a static mode. The method includes: in the spread spectrum mode, measuring phase jitter between the input clock and the feedback input clock to form a spread spectrum phase jitter measurement; in the static mode, measuring phase jitter between the input clock and the feedback input clock to form a static phase jitter measurement; and comparing the spread spectrum phase jitter measurement to the static phase jitter measurement to determine the dynamic phase offset.

Abstract: In accordance with one or more embodiments of the present invention, a system includes a phase-locked loop circuit that receives a reference signal and a feedback signal and provides an output signal. A control circuit also receives the reference signal and the feedback signal and provides a correction current for the phase-locked loop circuit to reduce a phase error of the output signal.

Abstract: A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.

Abstract: In one embodiment, a semiconductor device which generates a substantially constant reference voltage over a broad temperature range upon application of a power supply voltage thereto, wherein a current substantially inversely proportional to the value of a load resistor is drawn through the resistor to generate a substantially constant voltage across the resistor. The current through the resistor is the sum of a first current and a second current. The first current is determined by the absolute value of the threshold voltage of a depletion mode FET (DFET) in conjunction with an associated first resistor. The second current is determined by the threshold voltage of an enhancement mode FET (EFET) in conjunction with an associated second resistor. As the temperature of the device changes the first and second currents will change in opposite directions with the sum being changed inversely proportional to the change in resistance with temperature of the load resistor.

Abstract: A circuit constructed in accordance with this invention includes means for asynchronously forcing a flip-flop (70) or a register to a programmable logical state in response to an initialization input signal (I). In one embodiment, a D-type flip-flop (70) is provided having data input terminal (71), a clock input terminal (77), a data output terminal (103), an initialization input terminal (41), and a programming input terminal (11). When an initialization input signal I is received, a predefined output signal is immediately placed on the data output terminal (103). The predefined output signal is defined by the status of a fuse (13), which is opened, if desired, via the programming input terminal (11). When an initialization input signal is not received, the flip-flop (70) operates as a normal D-type flip-flop.

Abstract: A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.