Patents by Inventor Michael G. Haverty
Michael G. Haverty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11757026Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: GrantFiled: October 16, 2020Date of Patent: September 12, 2023Assignee: Google LLCInventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
-
Publication number: 20210036137Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: ApplicationFiled: October 16, 2020Publication date: February 4, 2021Inventors: Stephen M. CEA, Cory E. WEBER, Patrick H. KEYS, Seiyon KIM, Michael G. HAVERTY, Sadasivan SHANKAR
-
Patent number: 10840366Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: GrantFiled: October 3, 2019Date of Patent: November 17, 2020Assignee: Intel CorporationInventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
-
Publication number: 20200035818Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: ApplicationFiled: October 3, 2019Publication date: January 30, 2020Inventors: Stephen M. CEA, Cory E. WEBER, Patrick H. KEYS, Seiyon KIM, Michael G. HAVERTY, Sadasivan SHANKAR
-
Patent number: 10483385Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: GrantFiled: December 23, 2011Date of Patent: November 19, 2019Assignee: Intel CorporationInventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
-
Publication number: 20170162661Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: ApplicationFiled: February 17, 2017Publication date: June 8, 2017Applicant: INTEL CORPORATIONInventors: MICHAEL G. HAVERTY, SADASIVAN SHANKAR, TAHIR GHANI, SEONGJUN PARK
-
Patent number: 9577057Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: GrantFiled: October 19, 2015Date of Patent: February 21, 2017Assignee: INTEL CORPORATIONInventors: Michael G. Haverty, Sadasivan Shankar, Tahir Ghani, Seongjun Park
-
Publication number: 20160043191Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: ApplicationFiled: October 19, 2015Publication date: February 11, 2016Applicant: INTEL CORPORATIONInventors: MICHAEL G. HAVERTY, SADASIVAN SHANKAR, TAHIR GHANI, SEONGJUN PARK
-
Patent number: 9166004Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: GrantFiled: December 23, 2010Date of Patent: October 20, 2015Assignee: INTEL CORPORATIONInventors: Michael G. Haverty, Sadasivan Shankar, Tahir Ghani
-
Publication number: 20140209855Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.Type: ApplicationFiled: December 23, 2011Publication date: July 31, 2014Inventors: Stephen M. Cea, Cory E. Weber, Patrick H. Keys, Seiyon Kim, Michael G. Haverty, Sadasivan Shankar
-
Patent number: 8779589Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.Type: GrantFiled: December 20, 2010Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Harsono S. Simka, Daniel J. Zierath, Michael G. Haverty, Sadasivan Shankar
-
Patent number: 8633534Abstract: An apparatus comprises a substrate, a phonon-decoupling layer formed on the substrate, a gate dielectric layer formed on the phonon-decoupling layer, a gate electrode formed on the gate dielectric layer, a pair of spacers formed on opposite sides of the gate electrode, a source region formed in the substrate subjacent to the phonon-decoupling layer, and a drain region formed in the substrate subjacent to the phonon-decoupling layer. The phonon-decoupling layer prevents the formation of a silicon dioxide interfacial layer and reduces coupling between high-k phonons and the field in the substrate.Type: GrantFiled: December 22, 2010Date of Patent: January 21, 2014Assignee: Intel CorporationInventors: Michael G. Haverty, Sadasivan Shankar
-
Publication number: 20120161251Abstract: An apparatus comprises a substrate, a phonon-decoupling layer formed on the substrate, a gate dielectric layer formed on the phonon-decoupling layer, a gate electrode formed on the gate dielectric layer, a pair of spacers formed on opposite sides of the gate electrode, a source region formed in the substrate subjacent to the phonon-decoupling layer, and a drain region formed in the substrate subjacent to the phonon-decoupling layer. The phonon-decoupling layer prevents the formation of a silicon dioxide interfacial layer and reduces coupling between high-k phonons and the field in the substrate.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Inventors: Michael G. Haverty, Sadasivan Shankar
-
Publication number: 20120161321Abstract: Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulting layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.Type: ApplicationFiled: December 23, 2010Publication date: June 28, 2012Inventors: Michael G. Haverty, Sadasivan Shankar, Tahir Ghani, Seongjun Park
-
Publication number: 20120153478Abstract: Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.Type: ApplicationFiled: December 20, 2010Publication date: June 21, 2012Inventors: Harsono S. Simka, Daniel J. Zierath, Michael G. Haverty, Sadasivan Shankar
-
Publication number: 20070269646Abstract: A porous diamond dielectric material having a low dielectric constant and a method of forming such a material are described herein. A porous diamond dielectric material demonstrates high mechanical strength and has a low dielectric constant because of the presence of the pores. The dielectric constant is further decreased by the conversion of the sp2 type carbon bond terminations of the interior surface of the pores to sp3 type carbon bond terminations. This is accomplished by hydrogenation of the porous diamond dielectric material.Type: ApplicationFiled: May 18, 2006Publication date: November 22, 2007Inventors: Michael G. Haverty, K. V. Ravi, Sadasivan Shankar