Patents by Inventor Michael G. Khazhinsky
Michael G. Khazhinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9806521Abstract: A balun includes an input coil and an output coil with first and second outputs that vary during normal operation. The output coil has a center point connection that remains substantially constant during normal operation. An ESD circuit provides a low impedance path between the center point connection and chip ground when the voltage at the center point connection is above a first threshold voltage or below a second threshold voltage and isolates the center point connection from chip ground otherwise. Another ESD protection circuit provides ESD protection for other input or output terminals of the integrated circuit by selectively coupling the other input or output terminals to chip ground. Thus, a charge that builds up between one of the balun outputs and another terminal on the integrated circuit can be safely dissipated.Type: GrantFiled: October 29, 2014Date of Patent: October 31, 2017Assignee: Silicon Laboratories Inc.Inventors: Michael G. Khazhinsky, Ravi K. Kummaraguntla
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Publication number: 20160126725Abstract: A balun includes an input coil and an output coil with first and second outputs that vary during normal operation. The output coil has a center point connection that remains substantially constant during normal operation. An ESD circuit provides a low impedance path between the center point connection and chip ground when the voltage at the center point connection is above a first threshold voltage or below a second threshold voltage and isolates the center point connection from chip ground otherwise. Another ESD protection circuit provides ESD protection for other input or output terminals of the integrated circuit by selectively coupling the other input or output terminals to chip ground. Thus, a charge that builds up between one of the balun outputs and another terminal on the integrated circuit can be safely dissipated.Type: ApplicationFiled: October 29, 2014Publication date: May 5, 2016Inventors: Michael G. Khazhinsky, Ravi K. Kummaraguntla
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Patent number: 8009397Abstract: An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.Type: GrantFiled: June 13, 2008Date of Patent: August 30, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Melanie Etherton, Michael G. Khazhinsky, Eyal Melamed-Kohen, Valery Neiman
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Patent number: 7817387Abstract: An electrostatic discharge (ESD) protected circuit is coupled to a power supply voltage rail and includes a multiple independent gate field effect transistor (MIGFET), a pre-driver, and a hot gate bias circuit. The MIGFET has a source/drain path coupled between an output pad and the power supply voltage rail and has a first gate terminal and a second gate terminal. The pre-driver circuit has an output. The hot gate bias circuit is coupled to the first gate terminal of the MIGFET, and the output of the pre-driver circuit is coupled to the second gate terminal of the MIGFET. The hot gate bias circuit is configured to apply a bias voltage to the first gate terminal of the MIGFET during an ESD event that increases the breakdown voltage of the MIGFET so as to better withstand the ESD event.Type: GrantFiled: January 9, 2008Date of Patent: October 19, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Michael G. Khazhinsky, Leo Mathew, James W. Miller
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Patent number: 7777998Abstract: Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.Type: GrantFiled: September 10, 2007Date of Patent: August 17, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Michael A. Stockinger, Michael G. Khazhinsky, James W. Miller
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Publication number: 20090310266Abstract: An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.Type: ApplicationFiled: June 13, 2008Publication date: December 17, 2009Inventors: Melanie Etherton, Michael G. Khazhinsky, Eyal Melamed-Kohen, Valery Neiman
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Patent number: 7593202Abstract: An integrated circuit (300/400) includes first and second power domains and a bank of input/output (I/O) cells (305/405) coupled to the first and second power domains. The bank of I/O cells (305/405) includes a first plurality of active clamps (374/445) for the first power domain and a second plurality of active clamps (384/425) for the second power domain wherein the first (374/445) and second (384/425) pluralities of active clamps overlap along the bank of I/O cells. According to one aspect each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving an output signal referenced to a respective first power domain, and at least one ESD protection element (425, 445) for a respective second power domain. According to another aspect, each of the plurality of input/output cells (420, 440) has a bonding pad (421, 441) for receiving a respective output signal and at least one ESD protection element for each of a first power domain and a second power domain.Type: GrantFiled: November 1, 2005Date of Patent: September 22, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Michael G. Khazhinsky, Martin J. Bayer, James W. Miller, Bryan D. Preble
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Patent number: 7589945Abstract: An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.Type: GrantFiled: August 31, 2006Date of Patent: September 15, 2009Assignee: Freescale Semiconductor, Inc.Inventors: James W. Miller, Melanie Etherton, Michael G. Khazhinsky, Michael Stockinger
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Patent number: 7573114Abstract: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.Type: GrantFiled: August 29, 2008Date of Patent: August 11, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, Michael G. Khazhinsky
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Publication number: 20090174973Abstract: An electrostatic discharge (ESD) protected circuit is coupled to a power supply voltage rail and includes a multiple independent gate field effect transistor (MIGFET), a pre-driver, and a hot gate bias circuit. The MIGFET has a source/drain path coupled between an output pad and the power supply voltage rail and has a first gate terminal and a second gate terminal. The pre-driver circuit has an output. The hot gate bias circuit is coupled to the first gate terminal of the MIGFET, and the output of the pre-driver circuit is coupled to the second gate terminal of the MIGFET. The hot gate bias circuit is configured to apply a bias voltage to the first gate terminal of the MIGFET during an ESD event that increases the breakdown voltage of the MIGFET so as to better withstand the ESD event.Type: ApplicationFiled: January 9, 2008Publication date: July 9, 2009Inventors: Michael G. Khazhinsky, Leo Mathew, James W. Miller
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Publication number: 20090067104Abstract: Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.Type: ApplicationFiled: September 10, 2007Publication date: March 12, 2009Inventors: Michael A. Stockinger, Michael G. Khazhinsky, James W. Miller
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Publication number: 20080315315Abstract: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.Type: ApplicationFiled: August 29, 2008Publication date: December 25, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Leo Mathew, Michael G. Khazhinsky
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Patent number: 7446990Abstract: An ESD protection system for I/O cells of an integrated circuit. The I/O cells of a bank of cells include a first type of I/O cells having ESD trigger circuits and a second type of I/O cells having ESD clamp devices. In one embodiment, the ESD trigger circuits of the first type are located at the same area of an active circuitry floor plan as the area in the floor plan for the ESD clamp devices of the I/O cells of the second type.Type: GrantFiled: February 11, 2005Date of Patent: November 4, 2008Assignee: Freescale Semiconductor, Inc.Inventors: James W. Miller, Michael G. Khazhinsky, Michael Stockinger, James C. Weldon
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Patent number: 7432122Abstract: An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.Type: GrantFiled: January 6, 2006Date of Patent: October 7, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, Michael G. Khazhinsky
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Publication number: 20080062596Abstract: An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.Type: ApplicationFiled: August 31, 2006Publication date: March 13, 2008Applicant: Freescale Semiconductor, Inc.Inventors: James W. Miller, Melanie Etherton, Michael G. Khazhinsky, Michael Stockinger
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Patent number: 7301741Abstract: A rail clamp circuit (100) includes first and second power supply voltage rails, a multiple independent gate field effect transistor (MIGFET) (128), and an ESD event detector circuit (138). The MIGFET (128) has a source/drain path coupled between the first (112) and second (114) power supply voltage rails, and first and second gates. The ESD event detector circuit (138) is coupled between the first (112) and second (114) power supply voltage rails, and has first and second output terminals respectively coupled to the first and second gates of the MIGFET. In response to an electrostatic discharge (ESD) event between the first (112) and second (114) power supply voltage rails, the ESD event detector circuit (138) provides a voltage to the second gate to lower an absolute threshold voltage of the MIGFET (128) while providing a voltage to the first gate above the absolute threshold voltage so lowered, thereby making the MIGFET (128) conductive with relatively high conductivity.Type: GrantFiled: May 17, 2005Date of Patent: November 27, 2007Inventors: Michael G. Khazhinsky, Leo Mathew
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Patent number: 7236339Abstract: An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).Type: GrantFiled: April 21, 2005Date of Patent: June 26, 2007Assignee: Freescale Semiconductor, Inc.Inventors: James W. Miller, Michael G. Khazhinsky, Michael Stockinger
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Patent number: 6900970Abstract: An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).Type: GrantFiled: January 22, 2003Date of Patent: May 31, 2005Assignee: Freescale Semiconductor, Inc.Inventors: James W. Miller, Michael G. Khazhinsky, Michael Stockinger
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Patent number: 6879476Abstract: An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).Type: GrantFiled: January 22, 2003Date of Patent: April 12, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Michael G. Khazhinsky, James W. Miller, Michael Stockinger
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Publication number: 20040141268Abstract: An ESD protection circuit (81) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (24), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor (24) is to maximize the Vt1 of the N-channel transistor (24). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor (24) first occurs. In some embodiments, the ESD protection circuit (81) includes a diode (64) which provides an additional current path from the I/O pad 31 to a first power supply node (76).Type: ApplicationFiled: January 22, 2003Publication date: July 22, 2004Inventors: James W. Miller, Michael G. Khazhinsky, Michael Stockinger