Abstract: This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.

Abstract: This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.

Abstract: Various embodiments provide means by which a video signal, associated with a multi-region visual display intended for presentation on a single display screen, can be processed in a manner that enables separate regions to be ascertained, and then split off onto different display screens. Detection algorithms can process the video signal in a manner that detects the divisions between the different regions that are intended for display on a single display screen. Once the divisions are detected, the video signal is processed to split the separate regions onto different display screens.

Abstract: Various embodiments provide means by which a video signal, associated with a multi-region visual display intended for presentation on a single display screen, can be processed in a manner that enables separate regions to be ascertained, and then split off onto different display screens. Detection algorithms can process the video signal in a manner that detects the divisions between the different regions that are intended for display on a single display screen. Once the divisions are detected, the video signal is processed to split the separate regions onto different display screens.

Abstract: In an implementation of a display source divider, a video generation system generates a video display source that includes display data for multiple display regions on a display device. For example, a gaming system generates a video display source that includes display data partitioned display, where each region of the partitioned display corresponds to a different player of the gaming system. A display source divider receives the video display source and generates multiple video streams each corresponding to a different display region of the partitioned display.

Abstract: In an implementation of a display source divider, a video generation system generates a video display source that includes display data for multiple display regions on a display device. For example, a gaming system generates a video display source that includes display data for a partitioned display, where each region of the partitioned display corresponds to a different player of the gaming system. A display source divider receives the video display source and generates multiple video streams each corresponding to a different display region of the partitioned display.

Abstract: This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.

Abstract: A memory controller is utilized to overcome NAND flash memory's propensity for comprising bad blocks of memory. The memory controller utilizes minimal hardware and is essentially transparent to a device requesting access to the NAND memory. A NAND flash memory device is configured to comprise a set of main blocks of memory and a set of auxiliary blocks of memory. Each block is divided into pages of memory and each page includes metadata. The metadata includes a block status indicator, indicating whether a block is good or bad. When receiving a request to access a page in the NAND flash memory, if the block in which the page resides is good, that block is accessed. If the block is bad, auxiliary memory is searched until a block containing the address of the bad block in its metadata is found. The found block is accessed in lieu of the bad block.

Abstract: This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting the multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.

Abstract: In an implementation of a display source divider, a video generation system generates a video display source that includes display data for multiple display regions on a display device. For example, a gaming system generates a video display source that includes display data for a partitioned display, where each region of the partitioned display corresponds to a different player of the gaming system. A display source divider receives the video display source and generates multiple video streams each corresponding to a different display region of the partitioned display.

Abstract: Various embodiments provide means by which a video signal, associated with a multi-region visual display intended for presentation on a single display screen, can be processed in a manner that enables separate regions to be ascertained, and then split off onto different display screens. Detection algorithms can process the video signal in a manner that detects the divisions between the different regions that are intended for display on a single display screen. Once the divisions are detected, the video signal is processed to split the separate regions onto different display screens.

Abstract: In an implementation of a display source divider, a video generation system generates a video display source that includes display data for multiple display regions on a display device. For example, a gaming system generates a video display source that includes display data for a partitioned display, where each region of the partitioned display corresponds to a different player of the gaming system. A display source divider receives the video display source and generates multiple video streams each corresponding to a different display region of the partitioned display.

Abstract: A composite socket member for use with a prosthetic appliance for a residual limb which comprises an outer socket which defines an inner cavity generally conforming to the outer surface of a residual limb, an inner socket which defines an inner cavity and being adapted to receive said residual limb, with said inner socket conforming to the shape of said outer socket and when nested within the cavity of said outer socket defines an air space between the inner surface of said outer socket and the outer surface of said inner socket and an inflatable bladder being disposed between the inner surface of said outer socket and the outer surface of said inner socket. The inner socket contains at least one flex area in its side wall at a preselected weight-bearing location whereby upon inflation of said bladder, pressure is applied by said bladder against said side wall at said preselected weight-bearing location of the residual limb to control the movement and rotation stability of said prosthetic appliance.

Abstract: A composite socket member for use with a prosthetic appliance for a residual limb which comprises an outer socket which defines an inner cavity generally conforming to the outer surface of a residual limb, an inner socket which defines an inner cavity and being adapted to receive the residual limb, with the inner socket conforming to the shape of the outer socket and when nested within the cavity of the outer socket defines an air space between the inner surface of the outer socket and the outer surface of the inner socket and an inflatable bladder being disposed between the inner surface of the outer socket and the outer surface of the inner socket. The inner socket contains at least one opening through its side wall at a preselected weight-bearing location whereby upon inflation of the bladder, pressure is applied by the bladder through the side wall opening against the preselected weight-bearing location of the residual limb to control the movement and rotation stability of the prosthetic appliance.