Abstract: A spatial light modulator system includes a concentration layer including an array of optical concentrators, such that each concentrator concentrates a portion of an input light beam. A modulation layer includes an array of light modulators each in optical communication with one of the optical concentrators for modulating the portion of the input light beam. The light modulators are spaced apart from one another in the modulation layer to form gaps between adjacent ones of the light modulators. A coil of each light modulator can surround a Faraday element or core containing a Faraday material to control a magnetic state of a Faraday material responsive to control signals.

Abstract: A spatial light modulator system includes a concentration layer including an array of optical concentrators, such that each concentrator concentrates a portion of an input light beam. A modulation layer includes an array of light modulators each in optical communication with one of the optical concentrators for modulating the portion of the input light beam. The light modulators are spaced apart from one another in the modulation layer to form gaps between adjacent ones of the light modulators. A coil of each light modulator can surround a Faraday element or core containing a Faraday material to control a magnetic state of a Faraday material responsive to control signals.

Abstract: A spatial light modulator system includes a concentration layer including an array of optical concentrators, such that each concentrator concentrates a portion of an input light beam. A modulation layer includes an array of light modulators each in optical communication with one of the optical concentrators for modulating the portion of the input light beam. The light modulators are spaced apart from one another in the modulation layer to form gaps between adjacent ones of the light modulators. A coil of each light modulator can surround a Faraday element or core containing a Faraday material to control a magnetic state of a Faraday material responsive to control signals.

Abstract: A serial flash integrated circuit is provided with an integrated error correction coding (“ECC”) system that is used with an integrated volatile page memory for fast automatic data correction. The ECC code has the capability of correcting any one or two bit errors that might occur on a page of the flash memory array. One bit corrections are done automatically in hardware during reads or transfer to the page memory, while two-bit corrections are handled in external software, firmware or hardware. The ECC system uses a syndrome generator for generating both write and read syndromes, and an error trapper to identify the location of single bit errors using very little additional chip space. The flash memory array may be refreshed from the page memory to correct any detected errors. Data status is made available to the application prior to the data. The use of the ECC is optional.

Abstract: A method of driving a motor without initial back rotation includes the steps of identifying a rest position 22 of a storage medium 20, mapping the rest position of storage medium 20 to a motor drive sequence, and driving the motor with the motor drive sequence, thereby enabling motor start-up without back rotation. The method is applicable to unipolar and bipolar drive methods as well as inductive read type and magneto-resistive type heads.

Abstract: A programmable data sequencer transfers fixed length data blocks between variable length storage segments of a magnetic storage disk and a buffer memory within a data storage device. The data sequencer includes a stack memory for holding user byte count values read from a header field preceding each data sector having variable length split storage segments. Each byte count value indicates respective length of a following variable length storage segment, so that the storage capacity of each segment is dynamically determined by the data sequencer in real time by popping the user byte count value from the stack into a storage segment length counter and by counting down the count value within the segment length counter.

Abstract: A disk file subsystem is disclosed which utilizes a track address decoding circuit which converts the track address which is recorded on the magnetic media in Gray code according to a 1/6 (2,8) run-length-limited recording code to its corresponding binary track address.

Abstract: A miniature disk drive achieves storage densities of at least approximately 1700 tracks per inch per storage surface of a storage disk defining a series of radially extensive servo sectors embedded within circumferential zones of data tracks. The sectors are recorded at a constant data transfer rate while each zone has a data transfer rate adapted to disk radius. The drive includes a head and head positioner, a read preamplifier for amplifying analog signals read from, and for amplifying signals to be written to, a storage surface.

Abstract: An on-the-fly error correction method and apparatus for correcting a data block within a stream of substantially contiguous data blocks during a data decoding process, each block having a Reed-Solomon error syndrome calculated and appended during an encoding process.

Abstract: A disk data storage subsystem includes a head and disk assembly. A plurality of sectors in data tracks include a servo portion containing a prerecorded pattern of a plurality of repeating, time staggered, non-phase-coherent bursts, each burst having a predetermined integral fraction radial offset relative to the other bursts.

Abstract: A rotating disk data storage subsystem is disclosed for recording and retrieving data in blocks of predetermined finite length, each block of data including an error correction code syndrome portion calculated in accordance with a predetermined Galois field error correction algorithm. The subsystem includes a data controller including a unitary, cyclic error correction code syndrome generator/decoder for processing each incoming byte of the block in accordance with the said error correction algorithm in a manner which tests for the presence of any errors and which generates error values from which the errors may be located and corrected. A microprocessor controller has access to the data controller for testing to determine if the generator has determined the presence of an error for an incoming block, and if so, for obtaining the error values.

Abstract: An encoder-decoder apparatus is disclosed for encoding and decoding code words of a predetermined code scheme in which which ONE bits thereof are separated by at least d ZERO bits and not more than k ZERO bits, in a serial bit stream path from and to components of serial data words each being of n parallel data bits in a data word transmission path, wherein the number of bits of each code word bears a three to two relation with respect to the number of bits of each component of the data word, and where n equals an even integer.

Abstract: A high performance, low cost rotating disk data storage subsystem includes a head and disk assembly. A plurality of sectors in data tracks include a servo portion containing a prerecorded pattern of a plurality of repeating, time staggered, non-phase-coherent bursts, each burst having a predetermined integral fraction radial offset relative to the other bursts and having a constant frequency preamble field followed by a unique value field related to its burst spatial location.