Abstract: A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.

Abstract: A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

Abstract: A method includes associating each block of a plurality of blocks of a memory device with a corresponding frequency access group of a plurality of frequency access groups based on corresponding access frequencies, and performing scan operations on blocks of each of the plurality of frequency access groups using a scan frequency that is different from scan frequencies of other frequency access groups. A scan operation performed on a frequency access group with a higher access frequency uses a higher scan frequency than a scan operation performed on a frequency access group with a lower access frequency.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including identifying an amount of storage charge loss (SCL) that has occurred on an open block of the memory device, the open block having one or more erased pages, determining that the amount of SCL satisfies a threshold criterion corresponding to an acceptable amount of SCL to occur on the open block, and responsive to determining that the amount of SCL satisfies the threshold criterion, keeping the open block open for programming the one or more erased pages.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.

Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.

Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.

Abstract: A configuration setting manager of a memory device receives a request to perform an adjustment operation on a set of configuration setting values for the memory device, where each configuration setting value of the set of configuration setting values is stored in a corresponding configuration register of a set of configuration registers; determines a configuration adjustment definition associated with one or more configuration setting values of the set of configuration setting values; calculates an updated set of configuration setting values by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; and stores the updated set of configuration setting values in the corresponding configuration registers.

Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

Abstract: In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.

Abstract: In one embodiment, a system maintains metadata associating each block of a plurality of blocks of the memory device with a corresponding frequency access group, where each frequency access group is associated with a corresponding scan frequency. The system determines that a first predetermined time period has elapsed since a last scan operation performed with respect to one or more blocks of the memory device, where the first predetermined time period specifies a first scan frequency. The system selects, based on the metadata, at least one block from a first frequency access group associated with the first scan frequency. The system performs a scan operation with respect to the selected block.

Abstract: An asynchronous power loss (APL) event is detected at a memory device. A last written page is identified in the memory device in response to detecting the APL event. A count of zeros programmed in the last written page is determined. The count of zeros is compared to a threshold constraint to determine whether to perform a dummy write operation on the last written page.

Abstract: An amount of threshold voltage distribution shift is determined. The threshold voltage distribution shift corresponds to an amount of time after programming of a reference page of a block of a memory device. A program-verify voltage is adjusted based on the amount of threshold voltage distribution shift to obtain an adjusted program-verify voltage. Using the adjusted program-verify voltage, a temporally subsequent page of the block is programmed at a time corresponding to the amount of time after the programming of the reference page.

Abstract: Several embodiments of memory devices and systems with offset memory component automatic calibration error recovery are disclosed herein. In one embodiment, a system includes at least one memory region and calibration circuitry. The memory region has memory cells that read out data states in response to application of a current read level signal. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to one or more of a plurality of offset read level test signals, including a base offset read level test signal. The base offset read level test signal is offset from the current read level signal by a predetermined value. The calibration circuitry is further configured to output the determined read level offset value.

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

Abstract: Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.