Patents by Inventor Michael G. Ward
Michael G. Ward has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170194430Abstract: The present disclosure provides methods for forming nanowire spacers for nanowire structures with desired materials in horizontal gate-all-around (hGAA) structures for semiconductor chips. In one example, a method of forming nanowire spaces for nanowire structures on a substrate includes performing a lateral etching process on a substrate having a multi-material layer disposed thereon, wherein the multi-material layer including repeating pairs of a first layer and a second layer, the first and second layers each having a first sidewall and a second sidewall respectively exposed in the multi-material layer, wherein the lateral etching process predominately etches the second layer through the second layer forming a recess in the second layer, filling the recess with a dielectric material, and removing the dielectric layer over filled from the recess.Type: ApplicationFiled: December 30, 2016Publication date: July 6, 2017Inventors: Bingxi Sun WOOD, Michael G. WARD, Shiyu SUN, Michael CHUDZIK, Nam Sung KIM, Hua CHUNG, Yi-Chiau HUANG, Chentsau YING, Ying ZHANG, Chi-Nung NI, Lin DONG, Dongqing YANG
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Patent number: 9245547Abstract: Method and apparatus for a magnetic sensor device having a magnetic field sensing element to generate an output signal and a signal processing module coupled to the magnetic field sensing element, the signal processing module including a linearization module to apply a third order Taylor expansion term to the output signal generated by the magnetic field sensing element. An output module can receive the linearized signal from the linearization module and provide a device output signal.Type: GrantFiled: February 19, 2015Date of Patent: January 26, 2016Assignee: ALLEGRO MICROSYSTEMS, LLCInventors: Alexander Latham, Michael G. Ward
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Patent number: 8987102Abstract: Methods of forming a metal silicide region in an integrated circuit are provided herein. In some embodiments, a method of forming a metal silicide region in an integrated circuit includes forming a silicide-resistive region in a first region of a substrate, the substrate having the first region and a second region, wherein a mask layer is deposited atop the substrate and patterned to expose the first region; removing the mask layer after the silicide-resistive region is formed in the first region of the substrate; depositing a metal-containing layer on a first surface of the first region and a second surface of the second region; and annealing the deposited metal-containing layer to form a first metal silicide region in the second region.Type: GrantFiled: July 12, 2012Date of Patent: March 24, 2015Assignee: Applied Materials, Inc.Inventors: Michael G. Ward, Igor V. Peidous
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Patent number: 8802522Abstract: Methods for forming a device on a substrate are provided herein. In some embodiments, a method of forming a device on a substrate may include providing a substrate having a partially fabricated first device disposed on the substrate, the first device including a first film stack comprising a first dielectric layer and a first high-k dielectric layer disposed atop the first dielectric layer; depositing a first metal layer atop the first film stack; and modifying a first upper surface of the first metal layer to adjust a first threshold voltage of the first device, wherein the modification of the first upper surface does not extend through to a first lower surface of the first metal layer.Type: GrantFiled: July 25, 2011Date of Patent: August 12, 2014Assignee: Applied Materials, Inc.Inventors: Michael G. Ward, Igor V. Peidous, Sunny Chiang, Yen B. Ta, Andrew Darlak, Peter I. Porshnev, Swaminathan Srinivasan
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Patent number: 8736316Abstract: In one aspect, a current driver, includes an operational amplifier that includes a first input port configured to receive a reference signal and a second input port configured to receive a variable signal. The variable signal is a function of an output current of the current driver. The reference signal corresponds to a selected maximum output current of the current driver. The current driver also includes a feedback transistor comprising a gate coupled to the output of the operational amplifier and a summing junction coupled to a drain of the feedback transistor and configured to receive a signal from the drain to enable clamping of the output current of the current driver to the maximum output current when the variable signal exceeds the reference signal. The summing junction is coupled to a set of transistors configured to provide the output current of the current driver.Type: GrantFiled: October 12, 2012Date of Patent: May 27, 2014Assignee: Allegro Microsystems, LLCInventors: Virag V. Chaware, Michael G. Ward
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Publication number: 20140103963Abstract: In one aspect, a current driver, includes an operational amplifier that includes a first input port configured to receive a reference signal and a second input port configured to receive a variable signal. The variable signal is a function of an output current of the current driver. The reference signal corresponds to a selected maximum output current of the current driver. The current driver also includes a feedback transistor comprising a gate coupled to the output of the operational amplifier and a summing junction coupled to a drain of the feedback transistor and configured to receive a signal from the drain to enable clamping of the output current of the current driver to the maximum output current when the variable signal exceeds the reference signal. The summing junction is coupled to a set of transistors configured to provide the output current of the current driver.Type: ApplicationFiled: October 12, 2012Publication date: April 17, 2014Inventors: Virag V. Chaware, Michael G. Ward
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Patent number: 8629642Abstract: A control loop circuit for use in a closed-loop control system that controls a system such as a linear motor is presented. The control loop circuit includes a lead-lag compensator that features a lead compensation network configured to reduce output noise without substantially changing the effect of the lead compensation in the control system's frequency response.Type: GrantFiled: February 15, 2012Date of Patent: January 14, 2014Assignee: Allegro Microsystems, LLCInventors: Michael G. Ward, David J. Haas
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Publication number: 20130288465Abstract: Methods for filling high aspect ratio features are provided herein. In some embodiments, method of filling a high aspect ratio feature formed in a substrate includes implanting a first species using a first plasma into first surfaces of a first layer formed along the surfaces of the high aspect ratio feature to form implanted first surfaces such that a second species subsequently deposited atop the first layer has an increased mobility along the implanted first surfaces relative to the first surfaces, wherein the first layer substantially prevents the second species from diffusing completely through the first layer; and subsequently filling the high aspect ratio feature with the second species.Type: ApplicationFiled: April 12, 2013Publication date: October 31, 2013Applicant: APPLIED MATERIALS, INC.Inventors: IGOR PEIDOUS, MICHAEL G. WARD
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Patent number: 8542011Abstract: A magnetic field sensor includes a compensation loop coupled in series with normal circuit couplings in order to reduce a transient signal that would otherwise be generated when the magnetic field sensor experiences a high rate of change of magnetic field. In some embodiments, the magnetic field sensor is a current sensor responsive to a magnetic field generated by a current-carrying conductor.Type: GrantFiled: April 2, 2013Date of Patent: September 24, 2013Assignee: Allegro Microsystems, LLCInventors: Weihua Chen, Michael G. Ward
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Patent number: 8461782Abstract: A mechanism for assigning unique addresses to identical devices attached to a serial bus is presented. Each device has at least one output and is provided with a storage device to provide a configurable portion of a bus address having a fixed portion and a configurable portion. The device is further provided with circuitry, coupled to the storage device and the output, to determine a state of the output and use the state to configure the configurable portion. Once the configurable portion is configured, the bus address uniquely identifies the device. Such configuration allows more than one such device to be coupled to the same serial bus, e.g., an I2C bus.Type: GrantFiled: August 27, 2009Date of Patent: June 11, 2013Assignee: Allegro Microsystems, LLCInventors: Michael G. Ward, David J. Haas, William P. Taylor
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Patent number: 8451002Abstract: A magnetic field sensor includes a compensation loop coupled in series with normal circuit couplings in order to reduce a transient signal that would otherwise be generated when the magnetic field sensor experiences a high rate of change of magnetic field. In some embodiments, the magnetic field sensor is a current sensor responsive to a magnetic field generated by a current-carrying conductor.Type: GrantFiled: September 14, 2012Date of Patent: May 28, 2013Assignee: Allegro Microsystems, LLCInventors: Weihua Chen, Michael G. Ward
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Publication number: 20130026617Abstract: Methods of forming a metal silicide region in an integrated circuit are provided herein. In some embodiments, a method of forming a metal silicide region in an integrated circuit includes forming a silicide-resistive region in a first region of a substrate, the substrate having the first region and a second region, wherein a mask layer is deposited atop the substrate and patterned to expose the first region; removing the mask layer after the silicide-resistive region is formed in the first region of the substrate; depositing a metal-containing layer on a first surface of the first region and a second surface of the second region; and annealing the deposited metal-containing layer to form a first metal silicide region in the second region.Type: ApplicationFiled: July 12, 2012Publication date: January 31, 2013Applicant: APPLIED MATERIALS, INC.Inventors: MICHAEL G. WARD, IGOR V. PEIDOUS
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Publication number: 20130009638Abstract: A magnetic field sensor includes a compensation loop coupled in series with normal circuit couplings in order to reduce a transient signal that would otherwise be generated when the magnetic field sensor experiences a high rate of change of magnetic field. In some embodiments, the magnetic field sensor is a current sensor responsive to a magnetic field generated by a current-carrying conductor.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: ALLEGRO MICROSYSTEMS, INC.Inventors: Weihua Chen, Michael G. Ward
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Patent number: 8339134Abstract: A magnetic field sensor includes a compensation loop coupled in series with normal circuit couplings in order to reduce a transient signal that would otherwise be generated when the magnetic field sensor experiences a high rate of change of magnetic field. In some embodiments, the magnetic field sensor is a current sensor responsive to a magnetic field generated by a current-carrying conductor.Type: GrantFiled: October 8, 2010Date of Patent: December 25, 2012Assignee: Allegro Microsystems, Inc.Inventors: Weihua Chen, Michael G. Ward
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Publication number: 20120171855Abstract: Methods for forming a device on a substrate are provided herein. In some embodiments, a method of forming a device on a substrate may include providing a substrate having a partially fabricated first device disposed on the substrate, the first device including a first film stack comprising a first dielectric layer and a first high-k dielectric layer disposed atop the first dielectric layer; depositing a first metal layer atop the first film stack; and modifying a first upper surface of the first metal layer to adjust a first threshold voltage of the first device, wherein the modification of the first upper surface does not extend through to a first lower surface of the first metal layer.Type: ApplicationFiled: July 25, 2011Publication date: July 5, 2012Applicant: APPLIED MATERIALS, INC.Inventors: MICHAEL G. WARD, IGOR V. PEIDOUS, SUNNY CHIANG, YEN B. TA, ANDREW DARLAK, PETER I. PORSHNEV, SWAMINATHAN SRINIVASAN
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Publication number: 20120146570Abstract: A control loop circuit for use in a closed-loop control system that controls a system such as a linear motor is presented. The control loop circuit includes a lead-lag compensator that features a lead compensation network configured to reduce output noise without substantially changing the effect of the lead compensation in the control system's frequency response.Type: ApplicationFiled: February 15, 2012Publication date: June 14, 2012Applicant: ALLEGRO MICROSYSTEMS, INC.Inventors: Michael G. Ward, David J. Haas
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Publication number: 20120086444Abstract: A magnetic field sensor includes a compensation loop coupled in series with normal circuit couplings in order to reduce a transient signal that would otherwise be generated when the magnetic field sensor experiences a high rate of change of magnetic field. In some embodiments, the magnetic field sensor is a current sensor responsive to a magnetic field generated by a current-carrying conductor.Type: ApplicationFiled: October 8, 2010Publication date: April 12, 2012Applicant: ALLEGRO MICROSYSTEMS, INCInventors: Weihua Chen, Michael G. Ward
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Patent number: 8138708Abstract: A control loop circuit for use in a closed-loop control system that controls a system such as a linear motor is presented. The control loop circuit includes a lead-lag compensator that features a lead compensation network configured to reduce output noise without substantially changing the effect of the lead compensation in the control system's frequency response.Type: GrantFiled: November 26, 2008Date of Patent: March 20, 2012Assignee: Allegro Microsystems, Inc.Inventors: Michael G. Ward, David J. Haas
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Publication number: 20110055442Abstract: A mechanism for assigning unique addresses to identical devices attached to a serial bus is presented. Each device has at least one output and is provided with a storage device to provide a configurable portion of a bus address having a fixed portion and a configurable portion. The device is further provided with circuitry, coupled to the storage device and the output, to determine a state of the output and use the state to configure the configurable portion. Once the configurable portion is configured, the bus address uniquely identifies the device. Such configuration allows more than one such device to be coupled to the same serial bus, e.g., an I2C bus.Type: ApplicationFiled: August 27, 2009Publication date: March 3, 2011Inventors: Michael G. Ward, David J. Haas, William P. Taylor
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Publication number: 20100127655Abstract: A control loop circuit for use in a closed-loop control system that controls a system such as a linear motor is presented. The control loop circuit includes a lead-lag compensator that features a lead compensation network configured to reduce output noise without substantially changing the effect of the lead compensation in the control system's frequency response.Type: ApplicationFiled: November 26, 2008Publication date: May 27, 2010Inventors: Michael G. Ward, David J. Haas