Patents by Inventor Michael Haverty

Michael Haverty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240087881
    Abstract: Embodiments include semiconductor processing methods to form low-K films on semiconductor substrates are described. The processing methods may include flowing one or more deposition precursors to a semiconductor processing system, wherein the one or more deposition precursors include a silicon-containing precursor. The silicon-containing precursor may include a carbon chain. The methods may include generating a deposition plasma from the one or more deposition precursors. The methods may include depositing a silicon-and-carbon-containing material on the substrate from plasma effluents of the deposition plasma. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant less than or about 3.0.
    Type: Application
    Filed: August 26, 2022
    Publication date: March 14, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Michael Haverty, Shruba Gangopadhyay, Bo Xie, Yijun Liu, Ruitong Xiong, Rui Lu, Xiaobo Li, Li-Qun Xia, Lakmal C. Kalutarage, Lauren Bagby
  • Publication number: 20240087880
    Abstract: Embodiments include semiconductor processing methods to form low-? films on semiconductor substrates are described. The processing methods may include flowing one or more deposition precursors to a semiconductor processing system. The one or more deposition precursors may include a silicon-containing precursor that may be a cyclic compound. The methods may include generating a deposition plasma from the one or more deposition precursors. The methods may include depositing a silicon-and-carbon-containing material on the substrate from plasma effluents of the deposition plasma. The silicon-and-carbon-containing material as-deposited may be characterized by a dielectric constant less than or about 3.0.
    Type: Application
    Filed: August 26, 2022
    Publication date: March 14, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Shruba Gangopadhyay, Bhaskar Jyoti Bhuyan, Michael Haverty, Bo Xie, Li-Qun Xia, Rui Lu, Yijun Liu, Ruitong Xiong, Xiaobo Li, Lakmal C. Kalutarage, Lauren Bagby
  • Publication number: 20240071927
    Abstract: Methods of forming interconnects and electronic devices are described. Methods of forming interconnects include forming a tantalum nitride layer on a substrate; forming a ruthenium layer on the tantalum nitride layer; and exposing the tantalum nitride layer and ruthenium layer to a plasma comprising a mixture of hydrogen (H2) and argon (Ar) to form a tantalum doped ruthenium layer thereon. Apparatuses for performing the methods are also described.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 29, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Shinjae Hwang, Feng Chen, Muthukumar Kaliappan, Michael Haverty
  • Patent number: 11821070
    Abstract: Methods of depositing metal films comprising exposing a substrate surface to a first metal precursor followed by a non-oxygen containing reducing agent comprising a second metal to form a zero-valent first metal film are described. The reducing agent has a metal center that is more electropositive than the metal center of the first metal precursor. In some embodiments, methods of depositing ruthenium films are described in which a substrate surface is exposed to a ruthenium precursor to form a ruthenium containing film on the substrate surface followed by exposure to a non-oxygen containing reducing agent to reduce the ruthenium containing film to a zero-valent ruthenium film and generate an oxidized form of the reducing agent.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: November 21, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Nasrin Kazem, Muthukumar Kaliappan, Jeffrey W. Anthis, Michael Haverty
  • Publication number: 20230317516
    Abstract: Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a metal-carbonyl containing precursor to form a self-assembled monolayer (SAM) on metallic surfaces.
    Type: Application
    Filed: July 14, 2022
    Publication date: October 5, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Muthukumar Kaliappan, Michael Haverty, Bhaskar Jyoti Bhuyan, Mark Saly, Aaron Dangerfield, Michael L. McSwiney, Feng Q. Liu, Xiangjin Xie
  • Publication number: 20230295794
    Abstract: Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.
    Type: Application
    Filed: May 24, 2023
    Publication date: September 21, 2023
    Inventors: Lakmal C. Kalutarage, Bhaskar Jyoti Bhuyan, Aaron Dangerfield, Feng Q. Liu, Mark Saly, Michael Haverty, Muthukumar Kaliappan
  • Publication number: 20230268414
    Abstract: Embodiments of the disclosure provide methods and electronic devices comprising a work function layer comprising a material that forms a weak silicide. The electronic devices comprise a silicon layer with the work function layer thereon and a metal contact on the work function layer.
    Type: Application
    Filed: July 13, 2022
    Publication date: August 24, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Michael Haverty, Avgerinos V. Gelatos, Gaurav Thareja, Seshadri Ganguli
  • Publication number: 20230268415
    Abstract: Embodiments of the disclosure provide methods and electronic devices comprising a work function layer comprising a material that forms a conductive oxide with or without titanium. The electronic devices comprise a silicon layer with the work function layer thereon and a metal contact on the work function layer.
    Type: Application
    Filed: July 13, 2022
    Publication date: August 24, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Michael Haverty, Avgerinos V. Gelatos, Gaurav Thareja
  • Publication number: 20230268399
    Abstract: Embodiments of the disclosure provide methods and electronic devices comprising a work function layer comprising a material that does not form a silicide. The electronic devices comprise a silicon layer with the work function layer thereon and a metal contact on the work function layer.
    Type: Application
    Filed: July 13, 2022
    Publication date: August 24, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Michael Haverty, Avgerinos V. Gelatos, Muthukumar Kaliappan
  • Publication number: 20230253201
    Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).
    Type: Application
    Filed: April 14, 2023
    Publication date: August 10, 2023
    Applicants: Applied Materials, Inc., National University of Singapore
    Inventors: Chandan Kr Barik, Michael Haverty, Muthukumar Kaliappan, Cong Trinh, Bhaskar Jyoti Bhuyan, John Sudijono, Anil Kumar Tummanapelli, Richard Ming Wah Wong, Yingqian Chen
  • Patent number: 11702733
    Abstract: Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: July 18, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Lakmal C. Kalutarage, Bhaskar Jyoti Bhuyan, Aaron Dangerfield, Feng Q. Liu, Mark Saly, Michael Haverty, Muthukumar Kaliappan
  • Patent number: 11658025
    Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: May 23, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Chandan Kr Barik, Michael Haverty, Muthukumar Kaliappan, Cong Trinh, Bhaskar Jyoti Bhuyan, John Sudijono, Anil Kumar Tummanapelli, Richard Ming Wah Wong, Yingqian Chen
  • Patent number: 11626288
    Abstract: Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: April 11, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Raymond Hung, Mehul Naik, Michael Haverty
  • Publication number: 20230070489
    Abstract: Described are microelectronic devices and methods for forming interconnections in microelectronic devices. Embodiments of microelectronic devices include tantalum-containing barrier films comprising an alloy of tantalum and a metal dopant selected from the group consisting of ruthenium (Ru), osmium (Os), palladium (Pd), platinum (Pt), and iridium (Ir).
    Type: Application
    Filed: June 21, 2022
    Publication date: March 9, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Michael Haverty, Lu Chen, Muthukumar Kaliappan
  • Publication number: 20230034058
    Abstract: Methods for reducing interface resistance of semiconductor devices leverage dual work function metal silicide. In some embodiments, a method may comprise selectively depositing a metal silicide layer on an Epi surface and adjusting a metal-to-silicon ratio of the metal silicide layer during deposition to alter a work function of the metal silicide layer based on whether the Epi surface is a P type Epi surface or an N type Epi surface to achieve a Schottky barrier height of less than 0.5 eV. The work function for a P type Epi surface may be adjusted to a value of approximately 5.0 eV and the work function for an N type Epi surface may be adjusted to a value of approximately 3.8 eV. The deposition of the metal silicide layer on the Epi surface may be performed prior to deposition of a contact etch stop layer and an activation anneal.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Inventors: Raymond HUNG, Mehul NAIK, Michael HAVERTY
  • Publication number: 20220406595
    Abstract: Novel cyclic silicon precursors and oxidants are described. Methods for depositing silicon-containing films on a substrate are described. The substrate is exposed to a silicon precursor and a reactant to form the silicon-containing film (e.g., elemental silicon, silicon oxide, silicon nitride). The exposures can be sequential or simultaneous.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 22, 2022
    Applicants: Applied Materials, Inc., National University of Singapore
    Inventors: Chandan Kr Barik, Doreen Wei Ying Yong, John Sudijono, Cong Trinh, Bhaskar Jyoti Bhuyan, Michael Haverty, Muthukumar Kaliappan, Yingqian Chen, Anil Kumar Tummanapelli, Richard Ming Wah Wong
  • Publication number: 20220372616
    Abstract: Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.
    Type: Application
    Filed: May 7, 2021
    Publication date: November 24, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Lakmal C. Kalutarage, Bhaskar Jyoti Bhuyan, Aaron Dangerfield, Feng Q. Liu, Mark Saly, Michael Haverty, Muthukumar Kaliappan
  • Publication number: 20220230874
    Abstract: Chalcogen silane precursors are described. Methods for depositing a silicon nitride (SixNy) film on a substrate are described. The substrate is exposed to the chalcogen silane and a reactant to deposit the silicon nitride (SixNy) film. The exposures can be sequential or simultaneous. The chalcogen silane may be substantially free of halogen. The chalcogen may be selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).
    Type: Application
    Filed: January 18, 2021
    Publication date: July 21, 2022
    Applicants: Applied Materials, Inc., National University of Singapore
    Inventors: Chandan Kr Barik, Michael Haverty, Muthukumar Kaliappan, Cong Trinh, Bhaskar Jyoti Bhuyan, John Sudijono, Anil Kumar Tummanapelli, Richard Ming Wah Wong, Yingqian Chen
  • Publication number: 20210350219
    Abstract: A crested barrier memory device may include a first electrode, a first self- rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately ?0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.
    Type: Application
    Filed: July 20, 2021
    Publication date: November 11, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Milan Pesic, Shruba Gangopadhyay, Muthukumar Kaliappan, Michael Haverty
  • Publication number: 20210140041
    Abstract: Methods of depositing metal films comprising exposing a substrate surface to a first metal precursor followed by a non-oxygen containing reducing agent comprising a second metal to form a zero-valent first metal film are described. The reducing agent has a metal center that is more electropositive than the metal center of the first metal precursor. In some embodiments, methods of depositing ruthenium films are described in which a substrate surface is exposed to a ruthenium precursor to form a ruthenium containing film on the substrate surface followed by exposure to a non-oxygen containing reducing agent to reduce the ruthenium containing film to a zero-valent ruthenium film and generate an oxidized form of the reducing agent.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 13, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Nasrin Kazem, Muthukumar Kaliappan, Jeffrey W. Anthis, Michael Haverty