Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: Apparatus and methods are disclosed, such as those involving deskewing serial data transmissions. One such apparatus includes a plurality of receivers, each of which is configured to receive a serial data stream. Each of the receivers includes a shift register including a plurality of stages arranged in sequence to propagate a stream of characters. Each of the stages is configured to store a character, and shift the character to a next stage in response to a clock signal. The receiver also includes a multiplexer having a plurality of inputs, each of the inputs being electrically coupled to a respective one of the stages of the shift register, and to select one of the stages to generate an output such that the outputs of the multiplexers in the receivers are deskewed.

Abstract: A flexible engine for implementing digital signal processing (DSP) functions involving repeating various arithmetic/logical operations on a stream of data includes multiple programmable filter elements, at least one of which includes a microcode control program for internal control of the programmable filter element. The engine also includes programmable interconnection logic coupled to the programmable filter elements for selectively combining, scaling, and accumulating output values from the first plurality of programmable filter elements and selectively providing accumulated values as inputs to the first plurality of programmable filter elements. A filter controller coupled to the programmable filter elements and the programmable interconnection logic includes its own microcode control program for external control of the programmable filter elements and the programmable interconnection logic. Multiple engines can be combined to form larger, more powerful engines.

Abstract: A single-instruction multiple-data processor comprises at least two multiply-accumulator units and associated coefficient memories and data memories. Coefficient memory addresses are formed from a base address and data samples stored in the data memories.

Abstract: A digital filter uses memory to emulate a variable shift register. Data samples are stored in a memory. The data samples are read from the memory, multiplied with corresponding coefficients stored in the same or a different memory, logically shifted, and written back into the memory so as to emulate a variable shift register. The data samples can be logically shifted by one or more bits at a time.

Abstract: A micro-programmable digital filter includes a plurality of programmable filter elements, an instruction memory for storing a control program, at least one instruction decoder for programming the filter elements based on the control program, and arithmetic logic for selectively scaling and accumulating output values received from the filter elements and providing accumulated values as inputs to the filter elements. The filter elements are typically coupled in series so that a coefficient output from one filter element can be passed to an adjacent filter element for implementing longer filters. A separate instruction decoder may be included for each filter element. Execution of the separate instruction decoders is typically staggered so that the instruction decoders can share the instruction memory and an accumulator without collision. Each filter element can be programmed to implement a different filtering function, or multiple filter elements can be programmed to operate on a single filtering function.

Abstract: A micro-programmable filter (MFE) engine includes multiple programmable filter elements and a microcode controller. The filter elements can be configured, controlled, and combined in different ways to implement different types of filters. The MFE preferably supports multiple-execution instructions that allow a single instruction to perform multiple moves into accumulators for efficient data movement inside MFE.

Abstract: A digital filter uses memory to emulate a variable shift register. Data samples are stored in a memory. The data samples are read from the memory, multiplied with corresponding coefficients stored in the same or a different memory, logically shifted, and written back into the memory so as to emulate a variable shift register. The data samples can be logically shifted by one or more bits at a time.

Abstract: A micro-programmable filter (MFE) engine includes multiple programmable filter elements and a microcode controller. The filter elements can be configured, controlled, and combined in different ways to implement different types of filters. The MFE preferably supports multiple-execution instructions that allow a single instruction to perform multiple moves into accumulators for efficient data movement inside MFE.

Abstract: A micro-programmable digital filter includes a plurality of programmable filter elements, an instruction memory for storing a control program, at least one instruction decoder for programming the filter elements based on the control program, and arithmetic logic for selectively scaling and accumulating output values received from the filter elements and providing accumulated values as inputs to the filter elements. The filter elements are typically coupled in series so that a coefficient output from one filter element can be passed to an adjacent filter element for implementing longer filters. A separate instruction decoder may be included for each filter element. Execution of the separate instruction decoders is typically staggered so that the instruction decoders can share the instruction memory and an accumulator without collision. Each filter element can be programmed to implement a different filtering function, or multiple filter elements can be programmed to operate on a single filtering function.

Abstract: A flexible engine for implementing digital signal processing (DSP) functions involving repeating various arithmetic/logical operations on a stream of data includes multiple programmable filter elements, at least one of which includes a microcode control program for internal control of the programmable filter element. The engine also includes programmable interconnection logic coupled to the programmable filter elements for selectively combining, scaling, and accumulating output values from the first plurality of programmable filter elements and selectively providing accumulated values as inputs to the first plurality of programmable filter elements. A filter controller coupled to the programmable filter elements and the programmable interconnection logic includes its own microcode control program for external control of the programmable filter elements and the programmable interconnection logic. Multiple engines can be combined to form larger, more powerful engines.

Abstract: A system and method for encoding and transmitting data with a spread-spectrum packet-switched system. Data to be transmitted by a packet transmitter are encoded for privacy and to restrict intelligent receipt of the data to the intended recipient. The encoded data is demultiplexed into sub-data-sequence signals which are spread-spectrum processed and then combined as a multichannel spread-spectrum signal. The multichannel spread-spectrum signal is concatenated with a header to output a packet-spread-spectrum signal which is transmitted over radio waves to a packet receiver. The packet receiver obtains timing for the multichannel spread-spectrum signal from the header. The multichannel spread-spectrum signal is then despread and multiplexed as received-encoded data. The received-encoded data is decoded by the intended recipient and stored in a receiver memory for output.

Abstract: A spread-spectrum receiver for time sharing a correlator for simultaneously receiving a plurality of parallel spread-spectrum signals. A combined multiplicity of symbols includes a multiplicity of symbols, simultaneously occurring during a symbol-time duration, from a plurality of spread-spectrum signals. A demultiplexer demultiplexes a sequence of the combined multiplicity of symbols into a plurality of symbol registers. Each of the symbol registers stores the chip-sequence signals corresponding to the combined multiplicity of symbols which were sent to the particular symbol register. A multiplexer selects a symbol register, other than the symbol register selected by the demultiplexer. The multiplicity of chip-sequence signals stored in the selected symbol register by the multiplexer are compared by a comparator with a multiplicity of replicas of the chip-sequence signals used to generate the spread-spectrum signals.

Abstract: A system and method for encoding and transmitting data with a spread-spectrum packet-switched system. Data to be transmitted by a packet transmitter are encoded for privacy and to restrict intelligent receipt of the data to the intended recipient. The encoded data is demultiplexed into sub-data-sequence signals which are spread-spectrum processed and then combined as a multichannel spread-spectrum signal. The multichannel spread-spectrum signal is concatenated with a header to output a packet-spread-spectrum signal which is transmitted over radio waves to a packet receiver. The packet receiver obtains timing for the multichannel spread-spectrum signal from the header. The multichannel spread-spectrum signal is then despread and multiplexed as received-encoded data. The received-encoded data is decoded by the intended recipient and is stored in a receiver memory for output.

Abstract: A intelligent power management apparatus for use with a matched-filter. A multiplexer multiplexes shifted-in-phase chips and shifted-quadrature-phase chips from an in-phase-shift register and a quadrature-phase-shift register, respectively, to generate multiplexed chips. The multiplexed chips include alternating sets of shifted-in-phase chips and shifted-quadrature-phase chips. A controller generates a POWERDOWN signal when the multiplexed chips from a received-spread-spectrum signal are unlikely to have a particular-chip sequence. The controller generates an ACTIVATION signal when the multiplexed chips are likely to have the particular-chip sequence present. An adder tree generates a CORRELATION signal when the multiplexed chips have the particular-chip sequence and match or correlate with the settings of the adder tree.

Abstract: A intelligent power management apparatus for use with a matched-filter. A multiplexer multiplexes shifted-in-phase chips and shifted-quadrature-phase chips from an in-phase-shift register and a quadrature-phase-shift register, respectively, to generate multiplexed chips. The multiplexed chips include alternating sets of shifted-in-phase chips and shifted-quadrature-phase chips. A controller generates a POWERDOWN signal when the multiplexed chips from a received-spread-spectrum signal do not have a particular-chip sequence. The controller generates an ACTIVATION signal when the multiplexed chips have the particular-chip sequence present. An adder tree generates a CORRELATION signal when the multiplexed chips have the particular-chip sequence and match or correlate with the settings of the adder tree. A number of AND gates inhibit the multiplexed chips from passing to the adder tree when the POWERDOWN signal is present, and pass the multiplexed chips to the adder tree when the ACTIVATION signal is present.

Abstract: A system for reducing power in electronic systems blocks current paths by electrically isolating idle, targeted devices through switching off the various device's entire sets of pins from the rest of the electronic system. Solid state switches are connected to every pin of a targeted device. In one logic state a control signal will turn the switches on and thereby connect the targeted device to the remainder of the system. In another logic state, the control signal will isolate the targeted device.