Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When data received by the controller, from a host device or from a non-volatile memory of the data storage device, the controller maintains table tracking the location of the data. The table may include a current location of the data in a volatile memory of the controller or the data storage device as well as the current location of the data a latch of the non-volatile memory. The table may further associate the location with a logical block address, such that when the host device requests the data not yet programmed to the non-volatile memory or data that is part of a data relocation operation, the controller may utilize the table to locate the relevant data and provide the data to the host device.

Abstract: The present disclosure generally relates to aligning non-aligned data for more efficient data reading. Data for write commands does not always perfectly align, yet the data is written in order of write command receipt. In such cases, aligned chunks of data may be split into two word lines (WLs) due to the presence of previously received smaller chunks of data. Rather than writing the data in order, the smaller chunks of data, which are non-aligned, are held in a buffer and written later to ensure that any aligned chunks of data remain aligned when written to the memory device. Once sufficient smaller chunks or data have accumulated to be aligned, or upon a need to write the smaller chunks upon reaching a threshold, the smaller chunks are written together in a single WL so as to not cause non-alignment of aligned data.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a dataset management (DSM) hint, determine if a second physical memory range associated with a next read operation is located within a threshold number of physical block addresses (PBAs) to a first physical memory range associated with a current read operation, where the next read operation is provided by the DSM hint, and utilize at least a portion of a latency budget associated with the current read operation to optimize a read parameter of the first physical memory range.

Abstract: A data storage device includes a memory device, a random access memory (RAM) device, and a controller coupled to the memory device and the RAM device. The controller is configured to determine a workload type of the data storage device, determine to store at least a portion of a compressed logical to physical translation table (ZCAT) in the RAM device based on the workload type, and utilize a remaining portion of the RAM device to perform background operations. The controller is further configured to determine a persistence or temperature of the ZCAT, where the portion of the ZCAT stored to the RAM device is based on the persistence and/or the temperature of the ZCAT. The remaining portion of the ZCAT is stored in the HMB, where the remaining portion may update any out-of-date ZCAT entries.

Abstract: The present disclosure generally relates to determining host device read patterns and then matching autonomous defragmentation to the read pattern to reduce latency impact and avoid unnecessary write amplification (WA). Host devices tend to read data in similar sized chunks. Additionally, host devices tend to read certain data sequentially. Based upon the typical chunk size and data read, the data can be defragmented in sizes to match the typical host device read chunks, and the data defragmented can then be read sequentially within a same plane even if the defragmented data is on different dies. The data is defragmented without relying upon a host command to be presented. Background operation time is used to move updated data such that a future sequential read is supported.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a power loss event has occurred, determine that one or more blocks are in an erased state, examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block, and place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block. The controller is further configured to determine a first bit count of page0 for a SLC voltage for the block, determine a second bit count of page1 for a TLC voltage for the block, and classify the block as either a SLC erased block or a TLC erased block.

Abstract: Boot code is loaded to the data storage device controller in a flexible manner by being able to receive chunks of the boot code from two separate locations, the host memory buffer (HMB) and the memory device, which may be a NAND device. Part of the boot code may be received from the HMB and another part of the boot code may be received from the memory device. If either the HMB or the memory device can deliver the chunks faster than the other, then the controller can receive the chunks from the faster location and periodically confirm the speed of delivery to ensure the boot code latency is optimized. The controller is configured to track an HMB turnaround latency and derive whether a next request should be sent to the HMB or the memory device when the data is present in both the HMB and the memory device.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller comprises an XOR module, an ECC module, a scrambler, an encoder, and comparison logic. The controller is configured to retrieve data from the memory device, decode the retrieved data, execute XOR protection logic on the decoded data, encode the decoded data, and compare the encoded data to the retrieved data stored in the memory device.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to store XOR parity data in a host memory buffer (HMB) of a host device, monitor a health of the memory device, determine that a threshold corresponding to the health of one or more blocks of the memory device has been reached or exceeded, and copy the XOR parity data from the HMB to the memory device. The controller is further configured to receive a low power mode indication from the host device and enter the low power mode after copying the XOR parity data from the HMB to the memory device. The controller is further configured to correct read failures using the XOR parity data retrieved from the HMB.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller comprises an XOR module, an ECC module, a scrambler, an encoder, and comparison logic. The controller is configured to retrieve data from the memory device, decode the retrieved data, execute XOR protection logic on the decoded data, encode the decoded data, and compare the encoded data to the retrieved data stored in the memory device.

Abstract: Systems and methods for host system memory translation are disclosed. The memory system may send a logical-to-physical address translation table to the host system. Thereafter, the host system may send commands that include a logical address and a physical address (with the host system using the logical-to-physical address translation table previously sent to generate the physical address). After sending the table to the host system, the memory system may monitor changes in the table, and record these changes in an update table. The memory system may use the update table in determining whether to accept or reject the physical address sent from the host system in processing the host system command. In response to determining to reject the physical address, the memory system may internally generate the physical address using the logical address sent from the host system and a logical-to-physical address translation table resident in the memory system.

Abstract: In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a volatile memory configured to store a first copy of a control table associated with the non-volatile memory. The controller is configured to perform a first update of a portion of the first copy of the control table in response to a first request, to initiate a second update of a second copy of the control table at the non-volatile memory based on the first update, and to execute a second request for access to the non-volatile memory concurrently with of the second update. The controller is configured to perform non-blocking control sync operations and non-blocking consolidation operations asynchronously, wherein non-blocking consolidation operations are atomic operations that include concurrent evacuation and compaction of an update layer to a cached address translation table in the volatile memory.

Abstract: Systems and methods for host system memory translation are disclosed. The memory system may send a logical-to-physical address translation table to the host system. Thereafter, the host system may send commands that include a logical address and a physical address (with the host system using the logical-to-physical address translation table previously sent to generate the physical address). After sending the table to the host system, the memory system may monitor changes in the table, and record these changes in an update table. The memory system may use the update table in determining whether to accept or reject the physical address sent from the host system in processing the host system command. In response to determining to reject the physical address, the memory system may internally generate the physical address using the logical address sent from the host system and a logical-to-physical address translation table resident in the memory system.

Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a volatile memory configured to store a first copy of a control table associated with the non-volatile memory. The controller is configured to perform a first update of a portion of the first copy of the control table in response to a first request, to initiate a second update of a second copy of the control table at the non-volatile memory based on the first update, and to execute a second request for access to the non-volatile memory concurrently with of the second update. The controller is configured to perform non-blocking control sync operations and non-blocking consolidation operations asynchronously, wherein non-blocking consolidation operations are atomic operations that include concurrent evacuation and compaction of an update layer to a cached address translation table in the volatile memory.

Abstract: In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.