Abstract: A servo control circuit provides seamless transition between seek and track modes while enabling both rapid seek mode operation and accurate tracking. The control circuit includes an analog-to-digital converter having a non-linear characteristic. The non-linear characteristic provides disproportionately large control voltages to derive speed and settling in the seek mode and essentially linear control voltages in the track mode to provide low noise and accurate tracking operation.

Abstract: According to the invention a well-switching arrangement, with a semiconductor circuit including a switch having an input terminal, an output terminal and a body region and at least one comparator having a first input coupled to at least one of the terminals and a second input coupled to a positive voltage rail, and logic coupled to an output of the comparator and responsive to the output to selectively couple the body-well region to one of the terminals or to the positive voltage rail.

Abstract: A servo control circuit provides seamless transition between seek and track modes while enabling both rapid seek mode operation and accurate tracking. The control circuit includes an analog-to-digital converter having a non-linear characteristic. The non-linear characteristic provides disproportionately large control voltages to derive speed and settling in the seek mode and essentially linear control voltages in the track mode to provide low noise and accurate tracking operation.

Abstract: Methods and structures for ensuring the highly linear discharge of a capacitor used for slew rate control of a power driving stage from a maximum voltage to a minimum supply voltage, such as ground. A voltage ramp generator uses a single cascoded current source to achieve the linear ramp-down.

Abstract: Methods and structures for ensuring the highly linear discharge of a capacitor used for slew rate control of a power driving stage from a maximum voltage to a minimum supply voltage, such as ground. A voltage ramp generator uses a single cascoded current source to achieve the linear ramp-down.

Abstract: A current amplifier comprising an amplifier circuit with overall negative feedback and an output current amplification circuit. In one embodiment, a photodiode provides a current to be amplified and the amplifier circuit and the output current amplification circuit are implemented using MOS technology.

Abstract: A circuit for regulating the gain of a variable differential gain amplifier. In one embodiment, a fully differential amplifier amplifies the outputs of the variable gain amplifier. The outputs of the fully differential amplifier are applied to a three input comparator so that if either of the outputs are greater than a reference voltage, a control signal is generated which is used to regulate the gain of the variable gain amplifier. In other embodiments, an analog OR function is used as an input to a conventional two input comparator in place of the three input comparator. In another embodiment, outputs of the variable gain amplifier are passed through switches to a scaling circuit which either voltage divides or amplifies and combines the outputs before application to a comparator. In each case, known asymmetries can be compensated for by independent gain control of each of the outputs of the variable gain differential amplifier.

Abstract: An integrated circuit includes storage circuits comprising isolation transistors to which a certain bias voltage may be applied. The bias voltage is generated by a bias voltage generator. A boost circuit responds to initial bias voltage transition by generating a boost current that is applied to the isolation transistors with the transitioning bias voltage.

Abstract: Methods and structures for ensuring the highly linear discharge of a capacitor used for slew rate control of a power driving stage from a maximum voltage to a minimum supply voltage, such as ground. A voltage ramp generator uses a single cascoded current source to achieve the linear ramp-down.

Abstract: A device and method for selecting within a group of analog signals the one with the lowest or with the highest value. In one embodiment the device has a differential amplifier configuration having an input to receive a comparison signal, a plurality of inputs to receive analog signals and a corresponding plurality of outputs to provide digital voltage signals. This device also has at least one logic circuit having a plurality of input terminals, each connected to a corresponding output of the differential amplifier configuration, and having at least one output terminal.

Abstract: A method and circuit are disclosed for controlling the current level of a differential logic circuit having a current source, input transistors which perform current steering based upon the input to the differential logic circuit, and load transistors. The circuit includes a first transistor that forms a current mirror with the current source, a second transistor coupled to the load transistors so that the operating characteristics of the load transistors substantially match the operating characteristics of the second transistor, and current source circuitry coupled between the first and second transistors. The current level selected in the current source circuitry sets the current level in the differential logic circuit and the resistance of the load transistors so that the output voltage swing of the differential logic circuit stays within an acceptable range of voltages, regardless of the selected current level.

Abstract: A circuit for regulating the gain of a variable differential gain amplifier. In one embodiment, a fully differential amplifier amplifies the outputs of the variable gain amplifier. The outputs of the fully differential amplifier are applied to a three input comparator so that if either of the outputs are greater than a reference voltage, a control signal is generated which is used to regulate the gain of the variable gain amplifier. In other embodiments, an analog OR function is used as an input to a conventional two input comparator in place of the three input comparator. In another embodiment, outputs of the variable gain amplifier are passed through switches to a scaling circuit which either voltage divides or amplifies and combines the outputs before application to a comparator. In each case, known asymmetries can be compensated for by independent gain control of each of the outputs of the variable gain differential amplifier.

Abstract: A high-gain comparator has a built-in hysteresis offset voltage generation feature. The comparator is characterized as having several elements, including a differential amplifier pair that is provided with first and second input voltages, an offset voltage element that creates an offset voltage between the first and second elements of the differential amplifier pair, an output generation element operably coupled to the differential amplifier pair that generates an output voltage of the comparator which is indicative of a voltage difference between the first and second input voltages, and a control element operably coupled to the output signal that controllably adjusts the offset voltage from a first state to a second state in accordance with the output signal to create a hysteresis condition of the comparator.

Abstract: An integrated circuit includes a transconductance circuit having a bias current generator coupled to a power supply. The bias current generator may include a current mirror circuit having an input and an output, where a current at the output is proportional to a current at the input. A first constant current source in the transconductance circuit has a first electrode coupled to the power supply. The transconductance circuit also includes first and second transistors and a diode. The diode is forward biased by the bias current generator. The first transistor has a collector coupled to a second electrode of the first constant current source and to a signal output. The second transistor has a drain coupled to an emitter of the first transistor, a source coupled to a reference voltage and a gate coupled to a signal input. The diode has an anode coupled to a base of the first transistor and a cathode coupled to a constant voltage source.

Abstract: A driver circuit for a power device of a power driving stage is capable of providing slew rate control. The driver circuit includes the following elements: a charging source of current, a discharging source of current, a first switch, a second switch, a conductive device, a capacitive element, an amplifier, and the power device. Both the first and second switches receive a control signal. The elements of the driver circuit are configured such that the conductive device will conduct only when the following two conditions are met: the control signal is a certain logic level and the voltage generated by the amplifier is larger than a reference voltage. When the control signal transitions from a first to a second logic state, a charging current is delivered to the capacitive element, an output voltage of the driver circuit increased to the reference voltage, and a voltage on a control terminal of the power device also increases to a charge pump voltage level.

Abstract: A DC-to-DC converter includes an error amplifier; a ramp generator for generating a ramp signal at the first input of the error amplifier independent of the output of the error amplifier and so that the output of the error amplifier ramps up at a relatively slow rate to avoid overshoot of the desired output voltage of the converter during the start-up phase of the converter; and a ramp disable circuit for disabling the ramp signal upon reaching a value corresponding to the normal operating phase of the converter. The DC-to-DC converter preferably includes at least one power switch and pulse width modulation (PWM) control circuit cooperating with the power switch to provide a desired output voltage of the converter. The ramp generator in one embodiment comprises a current source and an external capacitor connected thereto. In yet another embodiment, the ramp generator may be provided by a staircase ramp generator comprising an amplifier and an integrating capacitor connected thereto.

Abstract: A voltage regulator with load pole stabilization is disclosed. The voltage regulator consists of an error amplifier, an integrator which includes a switched capacitor, a pass transistor, and a feedback circuit. In one embodiment, the integrator circuit includes an amplifier, a capacitor, and a switched capacitor which is driven by a voltage controlled oscillator. The voltage controlled oscillator changes its frequency of oscillation proportional to the output current. In another embodiment, the switched capacitor is driven by a current controlled oscillator whose frequency of oscillation is also proportional to the output current of the voltage regulator. When the output current demand is large, the controlled oscillators increase the frequency which decreases the effective resistance of the switched capacitor thereby changing the frequency of the zero to respond to the change in the load pole.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.