Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. Furthermore, reference voltages are provided to decoding circuits by using distributed resistors. The decoding circuits utilize a cell layout that allows data to bused into the cell through polysilicon that also operates as the gate of the decode input transistors. The decode input transistors are arranged in strands of abutting transistors which may be connected in series or in parallel. Moreover, the decode cell input transistors may all be of the same conductivity type.

Abstract: A resin extruder for supplying resin to flaws in laminated glass includes a casing forming a resin reservoir from which resin is dispensed through a nozzle by screwing inward a ram partially received in the casing and carrying a pressure gauge communicating with the reservoir.

Abstract: A self-calibrated analog-to-digital converter with a corrected output includes an analog modulator (18) for receiving an analog input voltage and outputting a pulse train having a value proportional to the analog input voltage. The pulse train is filtered by a digital filter (20) which has the output thereof input to a calibration module (24). The calibration module (24) is controlled by a calibration control circuit (28) and is operable to correct the output to account for offset and gain errors. Prestored calibration parameters in a register (30) are utilized for this compensation. In a self-calibration mode, the control circuit (28) is operable to control a calibration multiplexer (12) to select a zero-scale input voltage on a terminal (16) and a full-scale reference voltage on a terminal (14) for input to the modulator (18).

Abstract: A method for adjusting capacitances in a monolithic integrated circuit wherein it is desirable that the capacitances form a binarily-weighted sequence of values includes sequentially-connecting trim capacitors in parallel with a primary capacitor and determining as each trim capacitor is connected, whether the resultant parallel capacitance is larger or smaller than that of a reference capacitance. If the resultant capacitance is too large, the trim capacitor is disconnected, but otherwise is left connected. The process is repeated until each trim capacitor has been tried. For the purpose of adjusting the capacitance of the next-largest capacitance, the final resultant capacitance is connected in parallel with the reference capacitance to form a new reference capacitance. The procedure is then repeated with the next-largest primary capacitor until the final resultant capacitance associated with each primary capacitor has been adjusted.

Abstract: A dual-tone multiple frequency signal generator is provided for use with telecommunications systems, data transfer systems and other applications. The tone encoding system utilizes MOS/LSI integrated circuitry on a single chip powered directly by telephone line voltages. An electronic keyboard circuit provides synchronized pulses to decode single-pole, single-throw keyboard switches by row and column. A crystal-controlled oscillator generates a reference frequency which is divided according to the row and column of an activated keyboard switch to obtain two pulse signals having frequencies representative of the activated switch. The outputs of the divider circuitry are fed to a programmed logic array which generates two digitally coded signals each representing a sinusoidal waveform. A digital-to-analog ladder network converts the digitally coded signals to continuous sine waves, and an operational amplifier combines the sinusoidal waveforms to provide a dual-tone output.