Abstract: A laminate donor element can be used to transfer a composite of a metal grid and an electronically conductive polymer to a receiver sheet for use in various devices. The laminate donor element has a donor substrate, a metal grid that is disposed over only portions of the donor substrate, leaving portions of the substrate uncovered by the metal grid, and an electronically conductive polymer that covers the portions of the donor substrate that are uncovered by the metal grid. The composite of metal grid and electronically conductive polymer exhibits a peel force of less than or equal to 40 g/cm for separation from the donor substrate at room temperature. The resulting article has a substrate on which a reverse composite of the metal grid and electronically conductive polymer is disposed, which article can be incorporated into various devices.

Abstract: A laminate donor element can be used to transfer a composite of a metal grid and an electronically conductive polymer to a receiver sheet for use in various devices. The laminate donor element has a donor substrate, a metal grid that is disposed over only portions of the donor substrate, leaving portions of the substrate uncovered by the metal grid, and an electronically conductive polymer that covers the portions of the donor substrate that are uncovered by the metal grid. The composite of metal grid and electronically conductive polymer exhibits a peel force of less than or equal to 40 g/cm for separation from the donor substrate at room temperature. The resulting article has a substrate on which a reverse composite of the metal grid and electronically conductive polymer is disposed, which article can be incorporated into various devices.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Abstract: A laminate donor element can be used to transfer a composite of a metal grid and an electronically conductive polymer to a receiver sheet for use in various devices. The laminate donor element has a donor substrate, a metal grid that is disposed over only portions of the donor substrate, leaving portions of the substrate uncovered by the metal grid, and an electronically conductive polymer that covers the portions of the donor substrate that are uncovered by the metal grid. The composite of metal grid and electronically conductive polymer exhibits a peel force of less than or equal to 40 g/cm for separation from the donor substrate at room temperature.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Abstract: A laminate donor element can be used to transfer a composite of a metal grid and an electronically conductive polymer to a receiver sheet for use in various devices. The laminate donor element has a donor substrate, a metal grid that is disposed over only portions of the donor substrate, leaving portions of the substrate uncovered by the metal grid, and an electronically conductive polymer that covers the portions of the donor substrate that are uncovered by the metal grid. The composite of metal grid and electronically conductive polymer exhibits a peel force of less than or equal to 40 g/cm for separation from the donor substrate at room temperature.

Abstract: A laminate donor element can be used to transfer a composite of a metal grid and an electronically conductive polymer to a receiver sheet for use in various devices. The laminate donor element has a donor substrate, a metal grid that is disposed over only portions of the donor substrate, leaving portions of the substrate uncovered by the metal grid, and an electronically conductive polymer that covers the portions of the donor substrate that are uncovered by the metal grid. The composite of metal grid and electronically conductive polymer exhibits a peel force of less than or equal to 40 g/cm for separation from the donor substrate at room temperature. The resulting article has a substrate on which a reverse composite of the metal grid and electronically conductive polymer is disposed, which article can be incorporated into various devices.

Abstract: A soft lock mechanism controls access by multiple processes to a shared resource to make simultaneous access an unlikely event, while not necessarily preventing simultaneous access. Preferably, the soft lock contains a next_free_time field, specifying when the soft lock will next be available, and a lock_duration, specifying a sufficiently long interval for most accesses to the resource to complete. The lock is obtained by comparing the current time to next_free_time. If the current time is later than next_free_time, then the lock is obtained immediately, and next_free_time is updated to the current time plus lock_duration. If the current time is before next_free_time, then next_free_time is incremented by lock_duration, and the requesting process waits until the old next_free_time to obtain the lock. No action is required to release the lock.

Abstract: Systems and methods to perform a register access are described. A particular method includes receiving a data frame at a bridge element of a plurality of bridge elements in communication with a plurality of server computers. The data frame may include a register access request and may be forwarded from a controlling bridge in communication with the plurality of bridge elements. A register may be accessed and execution of the register access request may be initiated in response to receiving the data frame.

Abstract: An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.

Abstract: An operating system kernel includes an attach mechanism and a detach mechanism. In addition, processes are tagged with an access attribute identifying the process as either a client process or a server process. Based on the access attribute, the operating system kernel lays out the process local address space differently depending on whether the process is a client process or a server process. A server process can “attach” to a client process and reference all of the client process' local storage as though it were its own. The server process continues to reference its own process local storage, but in addition, it can reference the other storage, using the client process' local addresses. When access to the other storage is no longer needed, the server process can “detach” from the client process. Once detached, the other storage can no longer be referenced.

Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.

Abstract: A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.

Abstract: A method, apparatus, and computer program product are disclosed in a data processing system for providing a virtualized time base in a logically partitioned data processing system. A time base is determined for each one of multiple processor cores. The time base is used to indicate a current time to one of the processor cores for which the time base is determined. The time bases are synchronized together for the processor cores such that each one of the processor cores includes its own copy of a synchronized time base. For one of the processor cores, a virtualized time base is generated that is different from the synchronized time base but that remains synchronized with at least a portion of the synchronized time base. The processor core utilizes the virtualized time base instead of the synchronized time base for indicating the current time to the processor core. The synchronized time bases and the portion of the virtualized time base remaining in synchronization together.

Abstract: An apparatus, program product and method for tracking the state of a migrating logical partition. Embodiments may use the state to determine the readiness and/or appropriateness of a page of the logical partition for transferring. The state may include a value or other data used to track changes affecting the page or the relative ease and/or appropriateness of migrating the page. A page manager table with entries corresponding to the state of each page of the logical partition may be used to track the state while the logical partition continues to run during a migration.

Abstract: A soft lock mechanism controls access by multiple processes to a shared resource to make simultaneous access an unlikely event, while not necessarily preventing simultaneous access. Preferably, the soft lock contains a next_free_time field, specifying when the soft lock will next be available, and a lock_duration, specifying a sufficiently long interval for most accesses to the resource to complete. The lock is obtained by comparing the current time to next_free_time. If the current time is later than next_free_time, then the lock is obtained immediately, and next_free_time is updated to the current time plus lock_duration. If the current time is before next_free_time, then next_free_time is incremented by lock_duration, and the requesting process waits until the old next_free_time to obtain the lock. No action is required to release the lock.

Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.

Abstract: A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.

Abstract: An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.

Abstract: An apparatus and method provide simultaneous local and global addressing capabilities in a computer system. A global address space is defined that may be accessed by all processes. In addition, each process has a local address space that is local (and therefore available) only to that process. An address space processor is implemented in software to perform system functions that distinguish between local addresses and global addresses. In the preferred embodiments, the local address space has a size that is a multiple of the size of a segment of global address space. When the hardware indicates a page fault, the address space processor determines whether the address being translated is a local address or a global address. If the address is a local address, the address space processor uses a local directory to process the page fault. If the address is a global address, the address space processor uses a global directory to process the page fault.