Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.

Abstract: A method of, and apparatus for, decoupling a defective or otherwise non-operational memory block from the power lines of a memory device is disclosed. Defects which cause excessive current consumption in defective memory blocks can be repaired through this approach. Mass-production yields can be improved significantly.

Abstract: A method and apparatus for measuring threshold voltages associated with the EEPROM portion of a non-volatile DRAM (NVDRAM) memory cell. The DRAM node of the NVDRUM cell is charged to a high potential and allowed to discharge through the EEPROM transistor. Since the gate of the EEPROM is tied to the DRAM node, the DRAM node voltage, which is also the EEPROM gate-to-source voltage, will, if the NVDRAM is left alone, drop until the EEPROM transistor shuts off. The EEPROM gate-to-source voltage at any point in time along this discharge path is measured through an iterative process. First, timing signals are adjusted to specify the point in time at which the EEPROM voltage is to be measured. Then, during each iteration, the EEPROM voltage is charged up and allowed to the discharge. At the point in time along the discharge path specified by the timing signals, a reference voltage is compared with the EEPROM voltage to determine if the reference voltage is above or below the EEPROM voltage.

Abstract: In a non-volatile DRAM (NVDRAM) memory device comprised of NVDRAM cells, each comprising a DRAM cell and an EEPROM cell, a method and apparatus for the page recall of data whereby the page recall start address may be specified by the user through the memory device's external control pins. A page of memory cells is defined as all of the memory cells connected to a single word line. During any recall operation, data are recalled from EEPROM to DRAM in only one memory cell per bit line. The externally specified page recall start address is input onto an external pad. It is then transmitted through an address selector circuit into the inputs of a counter circuit. The outputs of the counter circuit serve as the page recall start address, which reenters the address selector circuitry to be transmitted to address decoding circuitry.