Patents by Inventor Michael J. Hogan

Michael J. Hogan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5657246
    Abstract: A video conference platform includes a graphical user interface for configuration and control of a video conference. In particular, the graphical user interface allows for "windows" type operations to control various aspects of the video conference, including initial configuration, camera control, and data transmission.
    Type: Grant
    Filed: March 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Vtel Corporation
    Inventors: Michael J. Hogan, Reed Howard Rinn
  • Patent number: 4871136
    Abstract: A cantilever shelf bracket assembly, of which the vertical wall engagement member, the horizontal platform and the overhanging retention member together define the respective inner end, bottom and top of a shelf receiving throat; a resilient cushion and interlock member adhered to the shelf with one leg extending between the shelf inner edge and the inner end of the throat, and the second leg being between the top of the shelf and the overhanging retention member; there being mutually facing interlock grooves extending in from the ends of the bracket, removable end caps and protrusions that interfit into the interlock grooves for securing the shelf in the bracket.
    Type: Grant
    Filed: August 10, 1987
    Date of Patent: October 3, 1989
    Assignee: Knape & Vogt Manufacturing Co.
    Inventors: Walter L. Bessinger, Michael J. Hogan
  • Patent number: 4459660
    Abstract: A microcomputer device is disclosed containing a ROM for program memory, a read/write memory, and a CPU in a single integrated circuit. Input/output ports, interrupt and operating mode controls are memory mapped in the same logical address space as the program and read/write memory. The read/write memory is an array of one-transistor type dynamic storage cells in which data bits are stored in capacitor; refresh of this dynamic RAM is accomplished in a manner transparent to the CPU by an automatically-incremented address counter. Each data bit uses two one-transistor cells in a balanced, complementary array.
    Type: Grant
    Filed: April 13, 1981
    Date of Patent: July 10, 1984
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey D. Bellay, Michael J. Hogan, Kevin C. McDonough, John W. Hayn