Abstract: In digital video compression, the output bit-streams from respective encoding devices, each of which has a quantization parameter being varied between coarser and finer values in accordance with the nature of the material being encoded, are multiplexed. The allocation of bit rate amongst the respective encoding devices is effected by using a measure of the relative quantization levels of the respective encoding devices to select the encoding device from which data is read.

Abstract: In digital video compression, the output bit-streams from respective encoding means, each of which has a quantization parameter being varied between coarser and finer values in accordance with the nature of the material being encoded, are multiplexed. The allocation of bit rate amongst the respective encoding means is effected by using a measure of the relative quantization levels of the respective encoding means to select the encoding means from which data is to be read.

Abstract: A video signal is coded for transmission in a restricted bandwidth by sub-dividing a frame of picture information into a set of constituent blocks, measuring the amount of picture activity in each block, sampling the information in each block at a rate related to the amount of picture activity in that block, and adding to the coded block a supplementary signal indicating the sampling rate used for the block. Thus a decision is made on a block-by-block basis as to whether the block is transmitted with full accuracy or whether it can be adequately reconstructed from the previous frames.

Abstract: A pseudo-random binary sequence generator comprises at least one shift register (S, T) arranged in a recirculating loop and having a plurality of logic gates (G) for logically combining the outputs of selected stages of the register to provide a pseudo-random sequence, and a multiplexer (M), having a p data inputs and q address inputs all connected to selected shift register stages, and which selects at any instant one of the p data input bits in accordance with the q-bit address word to provide the generator output. The number s of logic gates is especially high and is related to the total number r of shift register stages (r>p+q) by the expression: 2.sup.s .gtoreq.r.sup.2. Some of the shift register stages of the or each shift register are connected to selected data inputs of the multiplexer and others of the stages of the same shift register are connected to selected address inputs of the multiplexer.