Abstract: Methods and devices are disclosed for compensating for device property variations across a wafer. The method comprises determining an output of a first device based on an input and determining an output of a second device based on the input. The second device is located at a different position with respect to a center of the wafer than a position of the first device with respect to the center of the wafer. The method further comprises determining a difference between the output of the first device and the output of the second device, the difference arising at least in part from the difference in position of the first and second devices. The method further comprises altering the first device such that the output of the first device based on the input substantially matches the output of the second device based on the input.

Abstract: A method includes placing an imaging device in contact with a sample, irradiating the sample via an illuminator such that radiation scatters off of the structure, and providing the scattered radiation to a detector to generate a digital video signal. A processor then performs various operations including subtracting a sum of a black state value and a user-defined black level clamping value from the digital video signal to create subtracted image data, substituting negative values in the subtracted image data with a reference value to create modified image data, and amplifying the modified image data by a user-defined gain to create contrast enhanced image data.

Abstract: A robust ground traction (drive) assembly for remotely controlled vehicles, which not only operates smoothly on surfaces that are flat, but also upon surfaces that include rugged terrain, snow, mud, and sand, is provided. The assembly includes a sun gear and a braking gear. The sun gear is configured to cause rotational force to be applied to second planetary gears through a coupling of first planetary gears. The braking gear is configured to cause the assembly (or the second planetary gears) to rotate around the braking gear when an obstacle or braking force is applied.

Abstract: A sensor network may be configured to operate in extreme temperature environments. A sensor may be configured to generate a frequency carrier, and transmit the frequency carrier to a node. The node may be configured to amplitude modulate the frequency carrier, and transmit the amplitude modulated frequency carrier to a receiver.

Abstract: Some embodiments of the present invention describe an apparatus that includes an oscillator, a ramp generator, and an inverter. The apparatus includes an oscillator, an inverter, and a ramp generator. The oscillator is configured to generate a waveform comprising a low time and a high time. The inverter is configured to receive the waveform generated by the oscillator, and invert the waveform. The ramp generator configured to increase a gate control voltage of a transistor connected to a solar cell, and rapidly decrease the gate control voltage of the transistor. During the low time of the waveform, a measurement of a current and a voltage of the solar cell is performed as the current and voltage of the solar cell are transmitted through a first channel and to a second channel.

Abstract: A current source logic gate with depletion mode field effect transistor (“FET”) transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Abstract: An apparatus and method are provided for communicating over power lines. The apparatus includes a coupling modem that is situated between a power line and a device. The coupling modem is configured to demodulate a signal received from the power line into a sine signal and a cosine signal. The coupling modem is also configured to modulate a communicated bit stream received from the device into a transmitted signal in order to impose the transmitted signal onto the power line.

Abstract: An imager is provided for viewing subcutaneous structures. In an embodiment of the invention, the imager includes a camera configured to generate a video frame, and an adaptive nonlinear processor. The adaptive nonlinear processor is configured to adjust a signal of the video frame below a first threshold to a maximum dark level and to adjust the signal of the video frame above a second threshold to a maximum light level. The imager further includes a display, configured to display the processed video frame.

Abstract: An apparatus, method, and computer program that can learn a linear or non-linear transfer function are disclosed. In one embodiment, for example, a computer-implemented method may include creating a plurality of combinations for at least one input, and calculating an output for the plurality of combinations. The method may also include calculating an error based on the calculated output.

Abstract: Some embodiments of the present invention describe an apparatus that includes an oscillator, a ramp generator, and an inverter. The apparatus includes an oscillator, an inverter, and a ramp generator. The oscillator is configured to generate a waveform comprising a low time and a high time. The inverter is configured to receive the waveform generated by the oscillator, and invert the waveform. The ramp generator configured to increase a gate control voltage of a transistor connected to a solar cell, and rapidly decrease the gate control voltage of the transistor. During the low time of the waveform, a measurement of a current and a voltage of the solar cell is performed as the current and voltage of the solar cell are transmitted through a first channel and to a second channel.

Abstract: Some embodiments of the present invention describe an apparatus that includes an oscillator, a ramp generator, and an inverter. The apparatus includes an oscillator, an inverter, and a ramp generator. The oscillator is configured to generate a waveform comprising a low time and a high time. The inverter is configured to receive the waveform generated by the oscillator, and invert the waveform. The ramp generator configured to increase a gate control voltage of a transistor connected to a solar cell, and rapidly decrease the gate control voltage of the transistor. During the low time of the waveform, a measurement of a current and a voltage of the solar cell is performed as the current and voltage of the solar cell are transmitted through a first channel and to a second channel.

Abstract: A current source logic gate with depletion mode field effect transistor (“FET”) transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Abstract: An apparatus and method are provided for communicating over power lines. The apparatus includes a coupling modem that is situated between a power line and a device. The coupling modem is configured to demodulate a signal received from the power line into a sine signal and a cosine signal. The coupling modem is also configured to modulate a communicated bit stream received from the device into a transmitted signal in order to impose the transmitted signal onto the power line.

Abstract: Embodiments of the present invention describe an apparatus including an oscillator, a ramp generator, and an inverter. The oscillator is configured to generate a waveform comprising a low time and a high time. The inverter is configured to receive the waveform generated by the oscillator, and invert the waveform. The ramp generator is configured to increase a gate control voltage of a transistor connected to a solar cell, and rapidly decrease the gate control voltage of the transistor. During the low time, a measurement of a current and a voltage of the solar cell is performed. During the high time, a measurement of a current of a shorted cell and a voltage reference is performed.

Abstract: An apparatus and method are provided for communicating over power lines. The apparatus includes a coupling modem that is situated between a power line and a device. The coupling modem is configured to demodulate a signal received from the power line into a sine signal and a cosine signal. The coupling modem is also configured to modulate a communicated bit stream received from the device into a transmitted signal in order to impose the transmitted signal onto the power line.

Abstract: A high temperature communications circuit includes a power conductor for concurrently conducting electrical energy for powering circuit components and transmitting a modulated data signal, and a demodulator for demodulating the data signal and generating a serial bit stream based on the data signal. The demodulator includes an absolute value amplifier for conditionally inverting or conditionally passing a signal applied to the absolute value amplifier. The absolute value amplifier utilizes no diodes to control the conditional inversion or passing of the signal applied to the absolute value amplifier.

Abstract: An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

Abstract: Embodiments of the present invention describe an apparatus including an oscillator, a ramp generator, and an inverter. The oscillator is configured to generate a waveform comprising a low time and a high time. The inverter is configured to receive the waveform generated by the oscillator, and invert the waveform. The ramp generator is configured to increase a gate control voltage of a transistor connected to a solar cell, and rapidly decrease the gate control voltage of the transistor. During the low time, a measurement of a current and a voltage of the solar cell is performed. During the high time, a measurement of a current of a shorted cell and a voltage reference is performed.

Abstract: Some embodiments of the present invention describe an apparatus that includes an oscillator, a ramp generator, and an inverter. The apparatus includes an oscillator, an inverter, and a ramp generator. The oscillator is configured to generate a waveform comprising a low time and a high time. The inverter is configured to receive the waveform generated by the oscillator, and invert the waveform. The ramp generator configured to increase a gate control voltage of a transistor connected to a solar cell, and rapidly decrease the gate control voltage of the transistor. During the low time of the waveform, a measurement of a current and a voltage of the solar cell is performed as the current and voltage of the solar cell are transmitted through a first channel and to a second channel.

Abstract: A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300° C. to 500° C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines.