Abstract: A method and apparatus for reducing magnetic tracking error in the position and orientation determined in a magnetic tracking system having a magnetic field generator. In some embodiments, the measured position and orientation of a sensor is compared to an expected theoretical position and orientation. Any error is assumed to be from “floor distortion,” i.e., eddy currents in the floor caused by the magnetic field generated by the magnetic field transmitter. The floor distortion is modeled as being caused by eddy currents caused by a second magnetic field transmitter that is a reflection of the actual transmitter. An algorithm iteratively searches over a parameter space to minimize the difference between the measured position and orientation and the theoretical position and orientation, and applies a correction to the measured position and orientation. The measurements and corrections of the position and orientation run in real-time with no additional hardware or calibration required.

Abstract: The present invention relates to an apparatus including a self-regulating current source, which utilizes a switching regulator to provide high efficiency power conversion and a high-side current monitor, but instead of driving the feedback input with a voltage divider to set the output voltage, the self-regulating current source utilizes a high-side current sense resistor with an operational amplifier optimized for current sensing, to drive the feedback input to the switching regulator, thereby creating a self-regulating constant current source. By adjusting the gain of the operational amplifier, the user can directly set the optimized current needed for using the apparatus in a variety of deployment devices, including satellite and pyrotechnic applications.

Abstract: An amplifying apparatus appropriate for use in high radiation environments where the amplifier has one or more channels configured to produce one or more output power signals. Each channel has a low pass filter configured to receive an analog signal and produce a filtered analog signal. The low pass filter is configured to attenuate a frequency component of the analog signal having a frequency greater than a predetermined corner frequency. Each channel includes a linear amplifier coupled to the low pass filter and configured to receive the filtered analog signal produced by the low pass filter. The amplifier produces the output power signal that has a high voltage which is a linear multiple of the voltage of the filtered analog signal.

Abstract: A digital image capture device including circuits capable of measuring the distance between the image capture device and an imaged object allows the capture of three-dimensional data of the surface of the object facing the image capture device. The distance data is obtained by the addition of a flash unit, and very high resolution timers to multiple pixels within the image capture device to measure the time required for the flash to reflect from the object. Since the speed of light is constant, the distance from the flash to the object to the image capture device may be calculated from the delay for the light from the flash to reach the device. Multiple pixels may be used to construct a three-dimensional model of the surface of the object facing the image capture device. Multiple images including distance data may be taken in order to generate a complete three-dimensional model of the surface of the object.

Abstract: A digital image capture device including circuits capable of measuring the distance between the image capture device and an imaged object allows the capture of three-dimensional data of the surface of the object facing the image capture device. The distance data is obtained by the addition of a flash unit, and very high resolution timers to multiple pixels within the image capture device to measure the time required for the flash to reflect from the object. Since the speed of light is constant, the distance from the flash to the object to the image capture device may be calculated from the delay for the light from the flash to reach the device. Multiple pixels may be used to construct a three-dimensional model of the surface of the object facing the image capture device. Multiple images including distance data may be taken in order to generate a complete three-dimensional model of the surface of the object.

Abstract: Circuitry combines a first operand A.sub.0, a second operand A.sub.1, and a third operand X in a blend function to produce a result Z. The result Z has a value equal to X*A.sub.0 +(1-X)* A.sub.1. The circuitry includes a plurality of logic gates organized in rows. When performing the blend operation each logic gates selects either a bit of the first operand A.sub.0 or a bit of the second operand A.sub.1. The selection for each logic gate depends upon bits of the third operand X. More specifically, each of the plurality of rows of logic gates selects the first operand A.sub.0 as output when an associated bit of the third operand X is at logic 1, and selects the second operand A.sub.1 as output when the associated bit of the third operand X is at logic 0. In addition to output generated by the plurality of rows of logic gates, a correction term is generated. For the blend operation, the correction term generated is the second operand A.sub.1.

Abstract: A method for operating a digital computer in response to the occurrence of an exception is disclosed. The method provides for the examination both of the contents of a predetermined computer location and of the instruction code for the instruction causing the exception. The computer then utilizes the result of those examinations to determine the dismissibility of the exception. The computer transfers control to the next instruction after the instruction which caused the exception if that instruction is dismissible.

Abstract: In a computing system a method for performing a multiplication of a first multiplicand and a second multiplicand is presented. The computing system includes a plurality of registers, an instruction decoder, an arithmetic logic unit, and a preshifter. The first multiplicand is divided into a plurality of equal length sections. Each section includes "n" bits, where "n" is an integer greater than one. The second multiplicand is placed in a first register from the plurality of registers. A second register from the plurality of registers is cleared to zero. For each section from the plurality of sections, starting with a first section containing high order bits of the first multiplication and proceeding to a last section of the first multiplicand containing low order bits of the first multiplicand the following three substeps. First, when the low order bit of a current section is a "1", the contents of the first register are added to the contents of the second register via the arithmetic logic unit.

Abstract: An instruction is presented to the cache; the instruction includes a cache control specifier which identifies a type of data being requested. Based on the cache control specifier, one of a plurality of replacement schemes is selected for swapping a data block out of the cache.

Abstract: A low overhead way for insuring that only routines of sufficient privilege can execute on a secured page of memory in an hierarchial computer system, and for raising the privilege level of a low privilege process in an orderly and secure way is presented. This is done through the execution of a single "gateway" branch instruction standing between a procedure call by a lower privileged routine, such as a user program, and an operating system itself.

Abstract: A virtual memory system is used to control access to I/O device address space in accordance with a preferred embodiment of the present invention. In a virtual memory system, access to pages within a processor's address space are assigned to each application program. Each I/O device is assigned two pages of address space. One page is considered to be privileged, and the other unprivileged. Each I/O device register is associated with an address in each of the two pages of its I/O device address space. Address space is global. What is meant by global is that physical memory locations map to the same virtual memory space regardless of what process is running on the processor. Access codes accompanied by a write disable bit are used to control process access to various addresses.

Abstract: A computer and an instruction set are presented which allow for a number of assists to be easily incorporated into the computer, and which allow for an instruction set extension. The computer is designed to support instructions which move data between an assist and a location, although an assist's operation and design need not be defined at the computer's date of design. Instructions are mapped to a particular assist. Assist instructions can be either executed in hardware by an assist, or emulated in software via a trap.

Abstract: This disclosure relates to a wafer scale power interconnect system by which defective circuits on the wafer can be automatically disconnected from the power and ground lines supplied to each of the circuits. The disconnect device employs a gate between the power source and the circuit, which gate is controlled by a fuse that can be destroyed by an excessive current thereby opening the gate. The disconnect device may also be just such a fuse or a current limiter.

Abstract: This disclosure relates to a controlled selective power disconnect means for employment with the various circuits implemented on a crystalline wafer so that a particular circuit can be selectively disconnected when it has developed a defect or short or is unwanted in the system for other reasons. The disconnect means employs a gate between the power source and the circuit, which gate is controlled by a fuse that can be melted or blown by a power disconnect signal thereby opening the gate. An amorphous switch can also be used such that networks can expand or contract around defective chips as required by the particular task or tasks involved.