Abstract: A display may have a pixel array such as a liquid crystal pixel array. The pixel array may be illuminated with backlight illumination from a direct-lit backlight unit. The backlight unit may include an array of light-emitting diodes (LEDs) on a printed circuit board. The display may have a notch to accommodate an input-output component. Reflective layers may be included in the notch. The backlight may include a color conversion layer with a property that varies as a function of position. The light-emitting diodes may be covered by a slab of encapsulant with recesses in an upper surface.

Abstract: The present disclosure provides methods, devices, and systems for controlling access to a controlled area. The method may comprise receiving a credential identifier in an access controller associated with an entrance to the enclosed area, and then authenticating the credential identifier. The method may then comprise sending an unlock signal through a solid state relay within the access controller to power a lock associated with but external to the access controller to unlock a door at the entrance to the enclosed area when the credential identifier has been successfully authenticated.

Abstract: A method of forming a pelletized fertilizer includes combining a fertilizer material with an organic binder to form a wet mixture, and drying the wet mixture to form particles comprising the fertilizer material and the organic binder dispersed therein. The fertilizer material includes solid particles of langbeinite, and the organic binder includes at least one cellulose polymer in a solid phase or a liquid gel phase. The dried particles are coated with mineral oil to form coated particles. A pelletized fertilizer includes pellets comprising solid particles of langbeinite (and optionally, other fertilizer materials) interspersed with at least one cellulose polymer. A mineral oil coating is over the pellets.

Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission.

Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission.

Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission.

Abstract: The randomizer includes connection circuitry with a random connection layout to parallely couple each of a quantity of bits for each of a plurality of inputs of bit width n to multiple output bits of a respectively coupled output. Combinational circuitry combines at least a portion of each of the plurality of outputs associated with each of the plurality of inputs to create a single resultant output of random data having a bit width of the quantity n.

Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines that process on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission.

Abstract: A Method and Apparatus for Randomizer has been disclosed. In one implementation a sequence of randomized connections then exclusive-OR operations and then an adder produce a randomized output.

Abstract: A Method and Apparatus for Randomizer has been disclosed. In one implementation a sequence of randomized connections then exclusive-OR operations and then an adder produce a randomized output.

Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission.

Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission.

Abstract: A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a memory write burst command having a first frame that includes a corresponding opcode positioned in one of a first command slot or a second command slot. The memory write burst command may also include a number of subsequent frames for conveying a data payload, as specified for example, by the opcode. The control unit may be configured to generate a number of concurrent sequential memory write operations to the memory in response to receiving the memory write burst command.

Abstract: A Method and Apparatus for Randomizer has been disclosed. In one implementation a sequence of randomized connections then exclusive-OR operations and then an adder produce a randomized output.

Abstract: Methods of processing an aqueous solution comprising potassium sulfate and magnesium sulfate include crystallizing K2SO4, crystallizing recycle crystals, and mixing at least a portion of the recycle crystals with the aqueous solution. Systems for processing potassium sulfate and magnesium sulfate include a first crystallizer and a second crystallizer in fluid communication with the second mix tank. The second crystallizer is structured and adapted to precipitate recycle crystals from the concentrated liquor to form a potassium-depleted recycle brine. The recycle crystals precipitated in the second crystallizer have a composition suitable to be recycled to the first crystallizer to increase the production of SOP.

Abstract: Methods of processing an aqueous solution comprising potassium sulfate and magnesium sulfate include crystallizing K2SO4, crystallizing recycle crystals, and mixing at least a portion of the recycle crystals with the aqueous solution. Systems for processing potassium sulfate and magnesium sulfate include a first crystallizer and a second crystallizer in fluid communication with the second mix tank. The second crystallizer is structured and adapted to precipitate recycle crystals from the concentrated liquor to form a potassium-depleted recycle brine. The recycle crystals precipitated in the second crystallizer have a composition suitable to be recycled to the first crystallizer to increase the production of SOP.

Abstract: A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.

Abstract: Methods of processing an aqueous solution comprising potassium sulfate and magnesium sulfate include crystallizing K2SO4, crystallizing recycle crystals, and mixing at least a portion of the recycle crystals with the aqueous solution. Systems for processing potassium sulfate and magnesium sulfate include a first crystallizer and a second crystallizer in fluid communication with the second mix tank. The second crystallizer is structured and adapted to precipitate recycle crystals from the concentrated liquor to form a potassium-depleted recycle brine. The recycle crystals precipitated in the second crystallizer have a composition suitable to be recycled to the first crystallizer to increase the production of SOP.

Abstract: Methods of processing an aqueous solution comprising potassium sulfate and magnesium sulfate include crystallizing K2SO4, crystallizing recycle crystals, and mixing at least a portion of the recycle crystals with the aqueous solution. Systems for processing potassium sulfate and magnesium sulfate include a first crystallizer and a second crystallizer in fluid communication with the second mix tank. The second crystallizer is structured and adapted to precipitate recycle crystals from the concentrated liquor to form a potassium-depleted recycle brine. The recycle crystals precipitated in the second crystallizer have a composition suitable to be recycled to the first crystallizer to increase the production of SOP.

Abstract: A system includes a host device that may be configured to initiate memory requests to a system memory. The system also includes a memory controller that may be configured receive the memory requests and to format the memory requests into memory transactions that are conveyed to the memory device via a memory interface. The memory transactions include a plurality of memory write command types. Each memory write command type corresponds to a different respective schedule for conveying a corresponding data payload.