Abstract: An ATM switch with rate-limiting congestion control has a plurality of input ports, a plurality of output ports operatively associated with one or more data buffers, an output control and a switch fabric for switching data units from any of the input ports to any of the output ports on virtual connections. The ATM switch imposes and enforces transmission rate-limiting policies against the virtual connections when the backlog of data units for delivery to a particular output port reaches a particular level. The ATM switch may be arranged to exempt high priority data units from the imposed rate limitations and has a means to lift the rate limitations when the backlog has been sufficiently reduced.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.

Abstract: An ATM switch with rate-limiting congestion control has a plurality of input ports, a plurality of output ports operatively associated with one or more data buffers, an output control and a switch fabric for switching data units from any of the input ports to any of the output ports on virtual connections. The ATM switch imposes and enforces transmission rate-limiting policies against the virtual connections when the backlog of data units for delivery to a particular output port reaches a particular level. The ATM switch may be arranged to exempt high priority data units from the imposed rate limitations and has a means to lift the rate limitations when the backlog has been sufficiently reduced.

Abstract: An improved address handling circuit includes a temporary storage device for temporarily storing at least one current cell, including a header, for address processing. A virtual channel (VC) filter is coupled to the temporary storage device and includes a VC address storage device for storing at least one selected virtual channel identifier (VCI), corresponding VC matching data and a corresponding cell identifier. The VC filter compares data from the header of the at least one current cell with the selected VCI to identify cells matching the at least one VCI. The VC filter includes a VC matching device for indicating a match. A virtual path (VP) filter is coupled to the temporary storage device and includes a VP address storage device for storing at least one selected virtual path identifier (VPI), corresponding VP matching data and a corresponding cell identifier.