Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

Abstract: A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

Abstract: A method and apparatus for compressing relative addresses and for storage of compressed relative addresses. A relative virtual address is computed in a particular stage of a processor pipeline and then compressed according to one or more compression techniques for storage in a micro-operation storage. A compressed relative address is retrieved from one or more micro-operation entries of the micro-operation storage and an uncompressed virtual address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

Abstract: A method and apparatus for decompressing relative addresses. A compressed relative address is retrieved from one or more micro-operation entries of a micro-operation storage and an uncompressed relative address is reconstructed from the compressed relative address and an instruction pointer (IP) address associated with the head of the micro-operation storage line in which the compressed relative address was stored. IP-relative addresses may be computed in a manner similar to relative branch targets, then compressed and stored in one or more micro-operation entries of a micro-operation storage line to be reconstructed later according to an IP address associated with the respective micro-operation storage line in which their compressed counterpart was stored.

Abstract: An instruction pipeline in a microprocessor includes one or more of the pipelines maintaining a return buffer. Upon detecting a call instruction, a pipeline will push the return address onto its return buffer. The pipeline will then determine if the call instruction was detected by a second pipeline and will send the return address to the second pipeline if the call was not detected by the second pipeline. Upon detecting a return instruction, the pipeline will pop the return address at the top of its return buffer. The return address may then be used in the instruction pipeline. The pipeline will send a request to a third pipeline to fill its return buffer with entries from the third pipeline's return buffer. The pipeline will determine if the return instruction was detected by a second pipeline and will send the return address at the top of its return buffer to the second pipeline if the return was not detected by the second pipeline.

Abstract: An instruction pipeline in a microprocessor includes one or more of the pipelines maintaining a return buffer. Upon detecting a call instruction, a pipeline will push the return address onto its return buffer. The pipeline will then determine if the call instruction was detected by a second pipeline and will send the return address to the second pipeline if the call was not detected by the second pipeline. Upon detecting a return instruction, the pipeline will pop the return address at the top of its return buffer. The return address may then be used in the instruction pipeline. The pipeline will send a request to a third pipeline to fill its return buffer with entries from the third pipeline's return buffer. The pipeline will determine if the return instruction was detected by a second pipeline and will send the return address at the top of its return buffer to the second pipeline if the return was not detected by the second pipeline.

Abstract: A cold drink vendor in which a circuit employing a programmed microcomputer controls the drink dispensing procedures and can be easily set to vary drink size, amount of ice to be dispensed, carbonation levels of each selection and the mix of the syrup and water for each selection. The circuit is based on a constant flow rate variable time method of dispensing the beverage. Initially, switch banks set by a service person are interrogated to determine the size of the drink and amount of ice to be dispensed, and the time cycle to dispense the drink is adjusted accordingly. Upon the establishment of credit and the actuation of a selection switch, additional switchbanks are interrogated to determine whether the beverage selected is high carbonated, low carbonated or non-carbonated, and to determine when to start the corresponding syrup pump, in accordance with the syrup viscosity, and the drink is dispensed.