Patents by Inventor Michael J. Tsuk

Michael J. Tsuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10565325
    Abstract: Systems and methods are provided for simulating an electrical characteristic of an electronic device having input ports and output ports. A device frequency response data structure is accessed that contains data associated with a plurality of port-to-port frequency responses of the electronic device, each port-to-port frequency response being associated with a plurality of frequencies. A QR decomposition is performed based on data from the frequency response data structure. A subset of the port-to-port frequency responses is selected based on the QR decomposition. A set of common poles is identified using the selected subset of port-to-port frequency responses, and a model of time domain behavior of the electronic device is generated using the set of common poles.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: February 18, 2020
    Assignee: Ansys, Inc.
    Inventors: Michael J. Tsuk, Amit Hochman, Jacob K. White
  • Patent number: 10311177
    Abstract: A model synthesizer generates a state-space model of a structure from frequency domain parameters of the structure using a selected number of significant eigenvalues of a matrix derived from the frequency-domain parameters such that the quality of the fit of the model is improved. A matrix of the frequency-domain parameters is reshaped so as to improve performance of determination of the fit quality. Passivity violations in the model can be removed via regularization and error control such that the fit quality of the model after removal of the passivity violations is within a specified tolerance. Cholesky factorization can improve the performance of passivity violation detection. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 4, 2019
    Assignee: Ansys, Inc.
    Inventors: Michael J. Tsuk, Jacob K. White
  • Patent number: 10097239
    Abstract: Systems and methods are provided for constructing a physical transmission line system. Characteristic data associated with a transmission line system is received. A model of the transmission line system is built based on the characteristic data. Building a model of the transmission line system includes determining a characteristic admittance matrix based on the characteristic data, determining a propagation function matrix based on the characteristic data, calculating a linking matrix based on the characteristic admittance matrix and the propagation function matrix, and determining a state space model based on the characteristic admittance matrix and the linking matrix. A simulation is performed using the state space model to determine a physical characteristic, where the transmission line system is built or modified based on the simulation-determined physical characteristic.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: October 9, 2018
    Assignee: Ansys, Inc.
    Inventors: Michael J. Tsuk, Jacob K. White, J. Eric Bracken
  • Patent number: 9477792
    Abstract: A model synthesizer generates a state-space model of a structure from frequency domain parameters of the structure using a selected number of significant eigenvalues of a matrix derived from the frequency-domain parameters such that the quality of the fit of the model is improved. A matrix of the frequency-domain parameters is reshaped so as to improve performance of determination of the fit quality. Passivity violations in the model can be removed via regularization and error control such that the fit quality of the model after removal of the passivity violations is within a specified tolerance. Cholesky factorization can improve the performance of passivity violation detection. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 25, 2016
    Assignee: SAS IP, Inc.
    Inventors: Michael J. Tsuk, Jacob K. White
  • Patent number: 8892414
    Abstract: In various embodiment, a simulator includes an analysis module for extracting transmission-line parameters of a transmission-line system from a network-parameter representation thereof, using discontinuity-detection-based phase unwrapping without introducing artificial discontinuities, and a simulator module for simulating the response of the transmission-line system to an input based on the extracted transmission-line parameters.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: November 18, 2014
    Assignee: SAS IP, Inc.
    Inventors: Subramanian N. Lalgudi, Michael J. Tsuk
  • Patent number: 8504345
    Abstract: A simulator includes an analysis module for extracting a state-space model of response of a physical system to an input from a frequency-domain representation thereof, using a SVD, and singular vectors thereof, of a Loewner matrix derived from the frequency-domain representation, and a simulator module for simulating the response of the physical system in the time domain based on the extracted state-space model.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: August 6, 2013
    Assignee: SAS IP, Inc.
    Inventors: Michael J. Tsuk, Jacob K. White
  • Patent number: 7350292
    Abstract: A method for affecting an impedance of a portion of an electrical circuit loop in an electrical circuit apparatus includes providing an electrical circuit apparatus having at least a portion of an electrical circuit loop including at least one of at least one trace and at least one via, and providing a layer of magnetic material disposed adjacent at least one of the trace and the via. The trace and the via are operatively connected together to provide electrical communication. Dielectric material is disposed in an operative relationship adjacent at least one of the trace and the via. The layer of magnetic material is disposed in operative relationship near at least one of the trace and the via to affect the impedance of at least one of the trace, the via and the portion of the circuit loop formed by the trace and the via.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: April 1, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Michael J. Tsuk
  • Patent number: 7199671
    Abstract: In one embodiment, a clock generation system comprises first and second hot-swappable oscillator (HSO) devices that generate respective timing signals, a plurality of controllable attenuators for controllably attenuating one of the timing signals, a combiner for combining the timing signals, a redundant clock source (RCS) device for generating at least one clock for distribution to other circuits using an output of the combiner, and logic for switching which of the timing signals is attenuated in response to failure of one of the first and second HSO devices.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: April 3, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Daniel Wissell, Daniel A. Strickland, Michael J. Tsuk
  • Patent number: 6784531
    Abstract: A hexagonal conductor path layout for power and ground distribution planes in a multi-layer VLSI device. The invention reduces crosstalk between switching devices in signal nets by reducing impedance in the distribution planes. Impedance is reduced by providing more direct line current paths and providing maximum path change angles of less than ninety degrees. Reduced impedance causes reduced coupling between current flows which share a common path and hence less crosstalk.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: August 31, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael J. Tsuk, Colin E. Brench
  • Publication number: 20040078183
    Abstract: A method comprises exciting a system with an input having predetermined maximum and minimum input values, selecting time points t1 and tj in a system response having a plurality of maximum response values at time points ti and a plurality of minimum response values at time points tj. A maximum worst-case excitation input is generated. The maximum worst-case excitation input has a positive transition from the predetermined minimum input value to the predetermined maximum input value the at each time (T−t1), and a negative transition from the predetermined maximum input value to the predetermined minimum input value at each time (T−tj). The method further generates a minimum worst-case excitation input having a negative transition from the minimum input value to the maximum input value at each time (T−ti), and a positive transition from the maximum input value to the minimum input value at each time (T−tj).
    Type: Application
    Filed: October 21, 2002
    Publication date: April 22, 2004
    Inventors: Victor Drabkin, Christopher Lee Houghton, Isaac Kantorovich, Michael J. Tsuk
  • Publication number: 20030230791
    Abstract: A hexagonal conductor path layout for power and ground distribution planes in a multi-layer VLSI device. The invention reduces crosstalk between switching devices in signal nets by reducing impedance in the distribution planes. Impedance is reduced by providing more direct line current paths and providing maximum path change angles of less than ninety degrees. Reduced impedance causes reduced coupling between current flows which share a common path and hence less crosstalk.
    Type: Application
    Filed: June 13, 2002
    Publication date: December 18, 2003
    Inventors: Michael J. Tsuk, Colin E. Brench