Abstract: A frequency synthesizer of the type having a reference frequency source CPG, frequency reduction means PS which cancels pulses from a frequency to be reduced and a jitter compensation signal circuit arranged to compensate for any jitter in the output frequency that would otherwise be caused by each cancelled cycle. The jitter compensation signal is derived from a jitter-containing pulse train via a d.c. removal circuit DGR and an integrator INT. Additionally, a perturbation signal is injected by a control device CD which causes pulses to be added to and also to be subtracted, by PA and PS respectively, from the frequency to be reduced, the jitter caused by this addition and subtraction also being compensated for by the compensation signal circuit.

Abstract: A frequency synthesizer of the pulse cancellation type which predicts the phase jitter that will be caused by the pulse cancellation and generates a compensation signal C which precisely compensates for the phase jitter. The compensation signal is derived directly, from a pulse train in the synthesizer which itself contains jitter, via a d.c. removal circuit DCR and an analogue integrator INT.

Abstract: A frequency synthesizer of the type employing a cycle cancellation technique and providing a correction signal which at least reduces the jitter in the output frequency caused by each cancelled cycle. A control device (CD) causes cycles to be added (PA) and cancelled (PS) without affecting the average frequency (Fc). A compensation signal for the resultant jitter is also generated (DAC and I) which is combined with the correction signal in an adder (AS) and with the frequency control voltage signal from the phase comparator (PC) in a further adder (ASD).

Abstract: A frequency modulator circuit arrangement, comprising a phase modulator (1) having a carrier signal input (2) which is fed from a carrier signal generator (18) and a modulation signal input (3) which is fed from a modulation signal input terminal (6) via an integrated circuit (7), includes a controllable frequency divider (16) in the carrier signal path through the phase modulator enabling the arrangement to operate with input modulation signals containing d.c. components without the integrator circuit output signal reaching impossibly high values. If the integrator output signal exceeds a first threshold (at terminal 26), a D-type flip-flop (27) is tripped causing a switch 28 to close, reducing the charge in the integrator capacitor (10) via a resistor (22) and hence changing the phase shift produced by the phase modulator. The division factor of the divider is simultaneously changed for one or more divisions cycles to introduce a compensating steady phase shift.

Abstract: To derive information about the R.F. impedance (Z.sub.t) presented at a port (P) of an electrical network including a source of R.F. signals (for example, an antenna and an antenna tuning unit) without requiring an additional source of R.F. signals, a circuit is coupled to the port (P) successively in two different states. This circuit comprises auxiliary network means (N.sub.1, N.sub.2) and radio indicating means such as a radio receiver (Rx); in the two states, it presents at the port (P) different respective impedances (Z.sub.1, Z.sub.2) and has between the port (P) and the receiver (Rx) different gains (A.sub.1, A.sub.2), the values being selected so that there is no difference between the amplitudes and/or phases of the signals reaching the receiver (Rx) when said R.F. impedance (Z.sub.t) lies on a respective locus in the complex impedance plane. The loci may for example be defined so as to intersect at a point representing an impedance with which it is desired to equate said R.F. impedance (Z.sub.t).

Abstract: An electronic analog switching device comprises a differential operational amplifier (1) with a feedback circuit between its output (2) and its inverting (-) input such that its (low impedance) output voltage follows the input signal voltage applied to its non-inverting (+) input. The output voltage is sampled by a first switch (5) and the samples are passed to the device output (4) where, for example, they may be stored on a capacitor (7). The feedback circuit has two paths, one via a feedback impedance (9) and the other via the first switch (5) and a second switch (8) operated synchronously with the first switch by control means (6). The "on" impedance of the first switch (5) is greatly reduced by including it in the feedback circuit, and the further inclusion of the second switch (8) and the impedance (9) substantially eliminates unwanted transient voltages that would otherwise occur under some circumstances when the first switch operates.

Abstract: In a phase lock loop frequency synthesizer, a successive addition rate multiplier provides a correction signal for eliminating ripple in a frequency control signal applied to a variable frequency oscillator which produces the output frequency of the synthesizer. Ripple elimination is improved by means of a feedback loop by which any residual ripple is detected and the correction signal is automatically adjusted.

Abstract: A frequency synthesizer of the type which selects pulses from a clock pulse generator (21) to provide a lower output frequency Fo, the synthesizer including an accumulator (22) of the type which, for each input pulse thereto, adds a preselected increment Y to the accumulated value in the accumulator and gives an overflow pulse each time an accumulated value C (where C is equal to or greater than Y) is reached or exceeded and leaves any excess (residue) in the accumulator. In accordance with the invention, adjustable delay means are coupled to the accumulator output such that each output pulse is delayed by an amount which depends on the residue in the accumulator thereby providing a spectrally pure output frequency.

Abstract: A method and apparatus for deriving radio-frequency impedance information of an electrical network, for example, an aerial, by using a current converter for inducing a radio-frequency current into the network and a voltage converter for impressing a radio-frequency voltage on the network. By applying radio-frequency signals to the converters, the resultant signals present in the network may be detected by connecting a radio receiver to the network, from which detected signals the impedance may be derived. By directly connecting the radio receiver to the network, the radio-frequency energy applied to the network by the converters may be kept very small.

Abstract: A problem with phase modulators particularly when modulating high frequency signals with signals of audio frequency is that noise is generated during the production of a free running ramp signal and noise is present on the modulating signal so that accurate detection of the modulating signal is not possible. In order to avoid this problem a fast ramp signal is generated by charging a low value capacitor (12) from a constant current source (13) in response to the edge of an applied timing signal. The starting voltage of the ramp signal is related to the phase of a modulating signal derived from a source having a low output impedance (25). The ramp signal is applied to a level detector (16) having a defined switching level, which detector produces an output edge signal in response to the ramp signal traversing the switching level in a given direction.

Abstract: Phase comparison apparatus, for example for use in phase lock loop (PLL) systems, comprises a first and a second phase comparator. The first comparator has a high gain (e.g. 1000) and a narrow phase difference range (e.g. 5.degree.) and the second phase comparator has a substantially greater range (e.g. 720.degree.). The second phase comparator is automatically switched out when the apparatus is operating in the narrow range and the outputs of the two comparators are proportionately combined in such a way that the combined output characteristic is linear over the whole range covered by the apparatus. The lock-up time of a PLL system using the apparatus is reduced by 10 to 100 times and system noise due to the apparatus can be reduced to negligible proportions.

Abstract: A high gain digital phase comparator which in digital phase lock loop systems can give a thousand-fold reduction in ripple and close-in noise sideband amplitudes. The comparator is of the sample-and-hold type but the normal ramp reference waveform is replaced by a trapezoidal waveform with a very steep rising or falling slope generated by a trapezoidal waveform generator. This slope is sampled by a sampling circuit coupled to said generator and its steepness gives the increased gain of the phase comparator leading to the reduced noise and ripple. Additional logic and switching circuits are added to make the comparator operate only during a rising edge of the trapezoidal waveform.