Abstract: A method and on-chip architecture are disclosed for multiplexing signals from selected external interconnect buses to chip internal buses such that bus rerouting can be implemented programmably without substantially affecting timing relations between time-parallel signals of a rerouted bus. An on-chip switch matrix is provided having N input lines crossing with M output lines to provide N times M crosspoints. A plurality of substantially less than N times M programmable interconnect switches (PIP's) are distributed symmetrically among the N.multidot.M crosspoints such that a same first number of interconnect switches (PIP's) are found along each of the N input lines thereby providing equal loading on each input line. The plurality of programmable interconnect switches (PIP's) are further distributed among the N.multidot.M crosspoints such that a same second number of interconnect switches (PIP's) are found along each of the M output lines thereby providing equal loading on each output line.

Abstract: A method and on-chip architecture are disclosed for multiplexing signals from selected external interconnect buses to chip internal buses such that bus rerouting can be implemented programmably without substantially affecting timing relations between time-parallel signals of a rerouted bus. An on-chip switch matrix is provided having N input lines crossing with M output lines to provide N times M crosspoints. A plurality of substantially less than N times M programmable interconnect switches (PIP's) are distributed symmetrically among the N.multidot.M crosspoints such that a same first number of interconnect switches (PIP's) are found along each of the N input lines thereby providing equal loading on each input line. The plurality of programmable interconnect switches (PIP's) are further distributed among the N.multidot.M crosspoints such that a same second number of interconnect switches (PIP's) are found along each of the M output lines thereby providing equal loading on each output line.

Abstract: A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes an internal clock selector for selecting a CLB-internal clock and at least one register that is responsive to the selected CLB-internal clock. The configurable interconnect network includes clock-carrying longlines extending in different directions past each CLB for broadcasting clock signals. The broadcast clock signals can originate outside the programmable integrated circuit or such broadcast clock signals can be generated within one or more of the CLB's and thereafter broadcast by way of the clock broadcasting longlines to others of the CLB's.

Abstract: A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a lookup table having inputs and outputs, a first multiplexer means for applying a selected subset of CLB input signals to the lookup table inputs, and a second multiplexer means for routing lookup table output signals to selectable destinations. The first multiplexer means can programmably route input signals to the lookup table inputs from a variety of sources including first through fourth direct-connect receiving terminals distributed symmetrically about the CLB, first through fourth longline receiving terminals distributed symmetrically about the CLB, first through fourth general-interconnect receiving terminals distributed symmetrically about the CLB, and first through fourth feedback means distributed symmetrically within the CLB.

Abstract: A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a plurality of function lookup tables (LUT's) each defined by a bit storage area and a select means responsive to input signals for selecting a stored bit. The design includes first and second LUT's that share a same plurality of input signals where the output of one of the LUT's is connectable by direct connect means to an input of a further pair of LUT's.

Abstract: A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. The interconnect network has longlines and programmable interconnect points (PIP's). PIP's are symmetrical distributed in a partially populated fashion within the interconnect network such that a substantially same signal propagation delay develops for each signal routed along a program-selected longline from a CLB adjacent to that longline to an IOB adjacent to that longline.

Abstract: A programmable integrated circuit includes configurable logic blocks (CLB's), configurable input/output blocks (IOB's) and a configurable interconnect network for providing program-defined routing of signals between the CLB's and IOB's. Each CLB includes a plurality of function lookup tables (LUT's) each defined by a bit storage area and a select means responsive to input signals for selecting a stored bit. The design includes first and second LUT's where the first LUT output determines whether the output of the second LUT will be forwarded or replaced by another function output.

Abstract: A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path.

Abstract: A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path.

Abstract: A PLL is integrated on the same chip as a programmable logic circuit and interconnected therewith in any of several useful ways. In one aspect of the invention, the output frequency of the PLL may be connected to the clock input of registers in the programmable logic circuit. If the PLL performs frequency multiplication, the chip then becomes a high-speed state machine synchronized to a lower-frequency input clock. In another aspect of the invention, the signal present at different parts of the phase lock loop may be provided to inputs of the programmable logic circuit. In another aspect, outputs of the programmable logic circuit may be used to control the operation and/or characteristics of various components in the PLL. For example, if a counter is included in the phase lock loop for causing the loop to generate a frequency multiple of the input signal, the counter may be made programmable according to outputs of the state machine.

Abstract: A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path.

Abstract: A programmable voltage comparator having a programmable hysteresis function controlling the comparator's output relative to first and second comparator input voltage variables. The programmable voltage comparator comprises an inverting and non-inverting input for receiving a first and second input voltages and an output providing a logic state signal reflecting the amplitude of the inverting and non-inverting input voltages. The comparator includes level shift circuitry coupled to the inverting and non-inverting inputs for programmably shifting the amplitude of the voltages applied to the inverting and non-inverting inputs responsive to the logic state output of the comparator. In one embodiment, the comparator includes a differential amplifier having inverting and non-inverting outputs, wherein the level shift circuitry comprises a first level shift circuit coupled to the non-inverting voltage input and having a feedback element coupling to the non-inverting output.

Abstract: A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path.

Abstract: A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path.

Abstract: A programmable gate array with an improved interconnect structure facilitates multi-source networks, communication of signals long distances across the array, and creation of networks in a symmetrical interconnect structure. The interconnect includes direct connections for each configurable logic block in the array to eight neighbors, including adjacent configurable logic blocks and next adjacent configurable logic blocks. Also, the interconnect includes uncommitted long lines which are driven by outputs of configurable logic blocks but not committed through the interconnect to inputs of any specific logic block. Rather, the uncommitted long lines are committed to connections to other segments of the interconnect. The interconnect structure also includes staggered switching matrices at the intersections of the horizontal and vertical buses in the interconnect. Repowering buffers that are configurable in both directions are associated with bidirectional lines in the interconnect, and include a bypass path.

Abstract: A configurable logic array includes an array of configurable logic cells arranged in columns and rows. A plurality of input/output cells are arranged around the perimeter of the array, and provide interfaces to input/output pads on the chip. A configurable interconnect structure includes vertical buses between the columns of configurable logic cells, and horizontal buses between the rows of configurable logic cells. Thus, each configurable logic cell in a subset of the array, has four adjacent buses in the interconnect structure. The configurable logic cells in this subset of the array include input structures, having programmable inputs connected to the buses on all four sides of the cell. Also, combinational logic connected to the input structure generates logic signals in response to the selected input signals. Finally, the configurable logic cells include output structures connected to the combinational logic, and having programmable outputs connected to the buses on all four sides of the cell.