Patents by Inventor Michael John O'Loughlin

Michael John O'Loughlin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10541306
    Abstract: A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: January 21, 2020
    Assignee: Cree, Inc.
    Inventors: Michael John O'Loughlin, Lin Cheng, Albert Augustus Burk, Jr., Anant Kumar Agarwal, Alexander Suvorov
  • Patent number: 10403722
    Abstract: A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: September 3, 2019
    Assignee: Cree, Inc.
    Inventors: Michael John O'Loughlin, Lin Cheng, Albert Augustus Burk, Jr., Anant Kumar Agarwal
  • Patent number: 9903046
    Abstract: Single crystal silicon carbide epitaxial layer on an off-axis substrate are manufactured by placing the substrate in an epitaxial growth reactor, growing a first layer of epitaxial silicon carbide on the substrate, interrupting the growth of the first layer of epitaxial silicon carbide, etching the first layer of epitaxial silicon carbide to reduce the thickness of the first layer, and regrowing a second layer of epitaxial silicon carbide on the first layer of epitaxial silicon carbide. Carrot defects may be terminated by the process of interrupting the epitaxial growth process, etching the grown layer and regrowing a second layer of epitaxial silicon carbide. The growth interruption/etching/regrowth may be repeated multiple times. A silicon carbide epitaxial layer has at least one carrot defect that is terminated within the epitaxial layer.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: February 27, 2018
    Assignee: Cree, Inc.
    Inventors: Michael John O'Loughlin, Joseph John Sumakeris
  • Patent number: 9349797
    Abstract: The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (m?·cm2) and even more preferably less than 5 m?·cm2. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 m?·cm2 and even more preferably less than 7 m?·cm2. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 m?·cm2 and even more preferably less than 10 m?·cm2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: May 24, 2016
    Assignee: Cree, Inc.
    Inventors: Lin Cheng, Anant K. Agarwal, Michael John O'Loughlin, Albert Augustus Burk, Jr., John Williams Palmour
  • Patent number: 9112083
    Abstract: A semiconductor device is provided that includes a Group III nitride based superlattice and a Group III nitride based active region comprising at least one quantum well structure on the superlattice. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer. A Group III nitride based semiconductor device is also provided that includes a gallium nitride based superlattice having at least two periods of alternating layers of InXGa1-XN and InYGa1-YN, where 0?X<1 and 0?Y<1 and X is not equal to Y. The semiconductor device may be a light emitting diode with a Group III nitride based active region. The active region may be a multiple quantum well active region.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: August 18, 2015
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, James Ibbetson, Michael John Bergmann, Kathleen Marie Doverspike, Michael John O'Loughlin, Howard Dean Nordby, Jr., Amber Christine Abare
  • Publication number: 20140070230
    Abstract: A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: CREE, INC.
    Inventors: Michael John O'Loughlin, Lin Cheng, Albert Augustus Burk, JR., Anant Kumar Agarwal
  • Patent number: 8430960
    Abstract: Parasitic deposits are controlled in a deposition system for depositing a film on a substrate, the deposition system of the type defining a reaction chamber for receiving the substrate and including a process gas in the reaction chamber and an interior surface contiguous with the reaction chamber. Such control is provided by flowing a buffer gas between the interior surface and at least a portion of the process gas to form a gas barrier layer such that the gas barrier layer inhibits contact between the interior surface and components of the process gas. A deposition system for depositing a film on a substrate using a process gas includes a reaction chamber adapted to receive the substrate and the process gas. The system further includes an interior surface contiguous with the reaction chamber.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: April 30, 2013
    Assignee: Cree, Inc.
    Inventors: Joseph John Sumakeris, Michael James Paisley, Michael John O'Loughlin
  • Publication number: 20130026493
    Abstract: The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (m?·cm2) and even more preferably less than 5 m?·cm2. In another embodiment, the semiconductor device has a blocking voltage of at least 15 kV and an on-resistance of less than 15 m?·cm2 and even more preferably less than 7 m?·cm2. In yet another embodiment, the semiconductor device has a blocking voltage of at least 20 kV and an on-resistance of less than 20 m?·cm2 and even more preferably less than 10 m?·cm2. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), or a PIN diode.
    Type: Application
    Filed: February 6, 2012
    Publication date: January 31, 2013
    Applicant: CREE, INC.
    Inventors: Lin Cheng, Anant K. Agarwal, Michael John O'Loughlin, Albert Augustus Burk, JR., John Williams Palmour
  • Publication number: 20120298955
    Abstract: A semiconductor device is provided that includes a Group III nitride based superlattice and a Group III nitride based active region comprising at least one quantum well structure on the superlattice. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer. A Group III nitride based semiconductor device is also provided that includes a gallium nitride based superlattice having at least two periods of alternating layers of InXGa1-XN and InYGa1-YN, where 0?X<1 and 0?Y<1 and X is not equal to Y. The semiconductor device may be a light emitting diode with a Group III nitride based active region. The active region may be a multiple quantum well active region.
    Type: Application
    Filed: June 27, 2012
    Publication date: November 29, 2012
    Inventors: David Todd Emerson, James Ibbetson, Michael John Bergmann, Kathleen Marie Doverspike, Michael John O'Loughlin, Howard Dean Nordby, JR., Amber Christine Abare
  • Patent number: 8227268
    Abstract: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well stricture. The quantum well structure includes a first Group III nitride based barrier layer, a Group III nitride based quantum well layer on the first barrier layer and a second Group III nitride based barrier layer. A Group III nitride based semiconductor device and methods of fabricating a Group III nitride based semiconductor device having an active region comprising at least one quantum well structure are provided. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer.
    Type: Grant
    Filed: October 19, 2007
    Date of Patent: July 24, 2012
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, James Ibbetson, Michael John Bergmann, Kathleen Marie Doverspike, Michael John O'Loughlin, Howard Dean Nordby, Jr., Amber Christine Abare
  • Publication number: 20120052660
    Abstract: A method for locally controlling the stoichiometry of an epitaxially deposited layer on a semiconductor substrate is provided. The method includes directing a first reactant gas and a doping gas across a top surface of a semiconductor substrate and directing a drive gas and a second reactant gas against the substrate separately from the first reactant gas in a manner that rotates the substrate while introducing the second reactant gas at an edge of the substrate to control each reactant separately, thereby compensating and controlling depletion effects and improving doping uniformity in resulting epitaxial layers on the substrate.
    Type: Application
    Filed: November 7, 2011
    Publication date: March 1, 2012
    Applicant: CREE, INC.
    Inventors: Joseph John SUMAKERIS, Michael James PAISLEY, Michael John O'LOUGHLIN
  • Patent number: 8052794
    Abstract: A method for locally controlling the stoichiometry of an epitaxially deposited layer on a semiconductor substrate is provided. The method includes directing a first reactant gas and a doping gas across a top surface of a semiconductor substrate and directing a drive gas and a second reactant gas against the substrate separately from the first reactant gas in a manner that rotates the substrate while introducing the second reactant gas at an edge of the substrate to control each reactant separately, thereby compensating and controlling depletion effects and improving doping uniformity in resulting epitaxial layers on the substrate.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: November 8, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Joseph John Sumakeris, Michael James Paisley, Michael John O'Loughlin
  • Patent number: 7312474
    Abstract: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well structure. The quantum well structure includes a first Group III nitride based barrier layer, a Group III nitride based quantum well layer on the first barrier layer and a second Group III nitride based barrier layer. A Group III nitride based semiconductor device and methods of fabricating a Group III nitride based semiconductor device having an active region comprising at least one quantum well structure are provided. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: December 25, 2007
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, James Ibbetson, Michael John Bergmann, Kathleen Marie Doverspike, Michael John O'Loughlin, Howard Dean Nordby, Jr., Amber Christine Abare
  • Patent number: 7230274
    Abstract: Single crystal silicon carbide epitaxial layer on an off-axis substrate are manufactured by placing the substrate in an epitaxial growth reactor, growing a first layer of epitaxial silicon carbide on the substrate, interrupting the growth of the first layer of epitaxial silicon carbide, etching the first layer of epitaxial silicon carbide to reduce the thickness of the first layer, and regrowing a second layer of epitaxial silicon carbide on the first layer of epitaxial silicon carbide. Carrot defects may be terminated by the process of interrupting the epitaxial growth process, etching the grown layer and regrowing a second layer of epitaxial silicon carbide. The growth interruption/etching/regrowth may be repeated multiple times. A silicon carbide epitaxial layer has at least one carrot defect that is terminated within the epitaxial layer.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: June 12, 2007
    Assignee: Cree, Inc
    Inventors: Michael John O'Loughlin, Joseph John Sumakeris
  • Patent number: 7118781
    Abstract: A method for controlling parasitic deposits in a deposition system for depositing a film on a substrate, the deposition system defining a reaction chamber for receiving the substrate and including a process gas in the reaction chamber and an interior surface contiguous with the reaction chamber, includes flowing a buffer gas between the interior surface and at least a portion of the process gas to form a gas barrier layer such that the gas barrier layer inhibits contact between the interior surface and components of the process gas.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: October 10, 2006
    Assignee: Cree, Inc.
    Inventors: Joseph John Sumakeris, Michael James Paisley, Michael John O'Loughlin
  • Patent number: 6958497
    Abstract: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well structure. The quantum well structure includes a first Group III nitride based barrier layer, a Group III nitride based quantum well layer on the first barrier layer and a second Group III nitride based barrier layer. A Group III nitride based semiconductor device and methods of fabricating a Group III nitride based semiconductor device having an active region comprising at least one quantum well structure are provided. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: October 25, 2005
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, James Ibbetson, Michael John Bergmann, Kathleen Marie Doverspike, Michael John O'Loughlin, Howard Dean Nordby, Jr., Amber Christine Abare
  • Publication number: 20030006418
    Abstract: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well structure. The quantum well structure includes a first Group III nitride based barrier layer, a Group III nitride based quantum well layer on the first barrier layer and a second Group III nitride based barrier layer. A Group III nitride based semiconductor device and methods of fabricating a Group III nitride based semiconductor device having an active region comprising at least one quantum well structure are provided. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer.
    Type: Application
    Filed: May 7, 2002
    Publication date: January 9, 2003
    Inventors: David Todd Emerson, James Ibbetson, Michael John Bergmann, Kathleen Marie Doverspike, Michael John O'Loughlin, Howard Dean Nordby, Amber Christine Abare