Patents by Inventor Michael K. Ciraula
Michael K. Ciraula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11361819Abstract: A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.Type: GrantFiled: December 14, 2017Date of Patent: June 14, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Andrew Robison, Michael K. Ciraula, Eric Busta, Carson Donahue Henrion
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Patent number: 10644826Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.Type: GrantFiled: February 23, 2018Date of Patent: May 5, 2020Assignee: Advanced Micro Devices, Inc.Inventors: John Wuu, Samuel Naffziger, Michael K. Ciraula, Russell Schreiber
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Patent number: 10509752Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.Type: GrantFiled: April 27, 2018Date of Patent: December 17, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Russell Schreiber, John Wuu, Michael K. Ciraula, Patrick J. Shyvers
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Publication number: 20190332561Abstract: A data processing system includes a processing unit that forms a base die and has a group of through-silicon vias (TSVs), and is connected to a memory system. The memory system includes a die stack that includes a first die and a second die. The first die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads. The group of micro-bump landing pads are connected to the group of TSVs of the processing unit using a corresponding group of micro-bumps. The first die has a group of memory die TSVs. The subsequent die has a first surface that includes a group of micro-bump landing pads and a group of TSV landing pads connected to the group of TSVs of the first die. The first die communicates with the processing unit using first cycle timing, and with the subsequent die using second cycle timing.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Applicant: Advanced Micro Devices, Inc.Inventors: Russell Schreiber, John Wuu, Michael K. Ciraula, Patrick J. Shyvers
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Patent number: 10452505Abstract: A memory system includes a non-volatile memory unit, a content-addressable memory unit coupled to the non-volatile memory unit, and an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit. The non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit. The error injection logic in combination with the content addressable memory unit replaces a bit cell in the memory system. The memory system performs an evaluation of various error detection and correction techniques.Type: GrantFiled: December 20, 2017Date of Patent: October 22, 2019Assignee: Advanced Micro Devices, Inc.Inventor: Michael K. Ciraula
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Publication number: 20190268086Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.Type: ApplicationFiled: February 23, 2018Publication date: August 29, 2019Applicant: Advanced Micro Devices, Inc.Inventors: John Wuu, Samuel Naffziger, Michael K. Ciraula, Russell Schreiber
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Publication number: 20190189196Abstract: A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.Type: ApplicationFiled: December 14, 2017Publication date: June 20, 2019Inventors: Andrew ROBISON, Michael K. CIRAULA, Eric BUSTA, Carson Donahue HENRION
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Publication number: 20190188064Abstract: A memory system includes a non-volatile memory unit, a content-addressable memory unit coupled to the non-volatile memory unit, and an error injection logic unit coupled to the non-volatile memory unit and the content addressable memory unit. The non-volatile memory unit is programmed to allow a first error injection onto a first data word using the error injection logic unit. The error injection logic in combination with the content addressable memory unit replaces a bit cell in the memory system. The memory system performs an evaluation of various error detection and correction techniques.Type: ApplicationFiled: December 20, 2017Publication date: June 20, 2019Inventor: Michael K. CIRAULA
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Patent number: 10303398Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.Type: GrantFiled: October 26, 2017Date of Patent: May 28, 2019Assignee: Advanced Micro Devices, Inc.Inventors: John Wuu, Michael K. Ciraula, Russell Schreiber, Samuel Naffziger
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Publication number: 20190129651Abstract: A processing system includes a compute die and a stacked memory stacked with the compute die. The stacked memory includes a first memory die and a second memory die stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.Type: ApplicationFiled: October 26, 2017Publication date: May 2, 2019Inventors: John WUU, Michael K. CIRAULA, Russell SCHREIBER, Samuel NAFFZIGER
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Patent number: 9916246Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.Type: GrantFiled: August 16, 2016Date of Patent: March 13, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Carson Donahue Henrion, Michael K. Ciraula, Gregg Donley, Alok Garg, Eric Busta
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Publication number: 20180052770Abstract: A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.Type: ApplicationFiled: August 16, 2016Publication date: February 22, 2018Inventors: Carson Donahue Henrion, Michael K. Ciraula, Gregg Donley, Alok Garg, Eric Busta
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Patent number: 7417449Abstract: A system for testing integrated circuit storage structures on a semiconductor wafer. A test IC manufactured on a semiconductor wafer includes a test storage structure such as a random access memory structure, for example, and an access controller including one or more clock sources. In various embodiments, the clock sources may include a ring oscillator and a pulse width generator. These clock sources may be programmable to provide a clock signal having a variety of frequencies for accessing the storage structure. In one embodiment, the frequencies provided by the access controller may be higher than a frequency that can be supplied to the wafer from ATE. In another embodiment, the pulse width generator may be programmable to provide a pulse train having a variety of duty cycles.Type: GrantFiled: November 15, 2005Date of Patent: August 26, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Randal L. Posey, Michael K. Ciraula
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Patent number: 7355881Abstract: A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.Type: GrantFiled: November 22, 2005Date of Patent: April 8, 2008Assignee: Advanced Micro Devices, Inc.Inventors: Floyd L. Dankert, Victor F. Andrade, Randal L. Posey, Michael K. Ciraula, Alexander W. Schaefer, Jerry D. Moench, Soolin Kao Chrudimsky, Michael C. Braganza, Jan Michael Huber, Amy M. Novak
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Patent number: 7268591Abstract: A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2n locations. The memory subsystem includes an address decoder and rotation logic each coupled to receive bits of a first address having n address bits. The rotation logic is also coupled to receive m rotation bits indicating a number of locations the first address is to be shifted if the first address falls within a specified range of addresses. The rotation logic and the address decoder are configured to operate in parallel with each other. Address selection logic is coupled to receive a first plurality of outputs from the address decoder and a second plurality of outputs from the rotation logic and is further configured to select a second address based on the first and second pluralities of outputs.Type: GrantFiled: November 15, 2005Date of Patent: September 11, 2007Assignee: Advanced Micro Devices , Inc.Inventors: Jan-Michael Huber, Michael K. Ciraula
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Patent number: 7080170Abstract: An apparatus comprises a buffer comprising a plurality of entries, a plurality of age vectors, and a control circuit coupled to the buffer. Each of the age vectors corresponds to one or more of the entries. Responsive to data being provided to the buffer to be written to at least a first entry, the control circuit is configured to generate a first age vector. The first age vector corresponds to the first entry, and is indicative of which of the plurality of entries contain data that is older than the data being written to the first entry. The control circuit is configured to select an entry for reading responsive to the plurality of age vectors. The selected entry has an attribute used to select the selected entry, and other entries indicated as storing older data in the age vector corresponding to the selected entry do not have the attribute.Type: GrantFiled: September 3, 2003Date of Patent: July 18, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Gerald D. Zuraski, Jr., Brian D. McMinn, Michael K. Ciraula
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Patent number: 6873184Abstract: An apparatus comprises a buffer comprising a plurality of entries, an insert pointer, a delete pointer, a plurality of first control circuits coupled to the buffer, and a second control circuit coupled to the buffer. The entries are logically divided into a plurality of groups. Each of the first control circuits corresponds to a respective group and selects an entry from the respective group for potential reading from the buffer. Furthermore, each of the first control circuits, in the event that the delete pointer indicates a first entry in the respective group and the insert pointer wraps around the buffer and indicates a second entry in the respective group, selects the first entry if the first entry is eligible for selection. The second control circuit selects a first group, and the entry selected from the first group by the first control circuits is the entry read from the buffer.Type: GrantFiled: September 3, 2003Date of Patent: March 29, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Brian D. McMinn, Michael K. Ciraula, Gerald D. Zuraski, Jr.
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Patent number: 5615168Abstract: A method and apparatus for providing single clock cycle pipelined access of a memory system, which combines synchronization and self resetting techniques, includes an array of memory cells that are arranged into columns and rows and intercoupled by bit lines and word lines. The memory system also includes an address decoder and a sense enable circuit. The address decoder, upon receiving an address, interprets the address to enable a particular word line, or word lines, and to disable precharging of a bit line, or bit lines. With the word line active, the sense enable circuit generates a sense enable signal when the clock signal has encountered a transitional edge, or is in an active state. When the sense enable signal is active, the sense amplifier reads the data from the addressed memory cell via the bit lines to produce output data.Type: GrantFiled: October 2, 1995Date of Patent: March 25, 1997Assignee: International Business Machines CorporationInventors: George M. Lattimore, Michael K. Ciraula, Manoj Kumar, Joseph M. Poplawski, Jr., Dieter F. Wendel, Friedrich Wernicke
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Patent number: 5592426Abstract: An extended segmented precharge architecture for static random access memories includes a logic circuitry on an SRAM chip to keep track as to whether a given bit line has been read out. As long as a given bit line has not been read out, precharge of the equalization lines is eliminated thereby increasing access cycle time and reducing power dissipation. The architecture can be applied to any size SRAM of any organization.Type: GrantFiled: April 27, 1995Date of Patent: January 7, 1997Assignee: International Business Machines CorporationInventors: Derwin L. Jallice, Christopher M. Durham, Michael K. Ciraula
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Patent number: 5566130Abstract: A logic filtered address transition detection circuit that receives a chip select signal and an ATD pulse, and which produces an internal clock pulse using:an AND gate, a filtered input terminal, a delay unit and a comparator unit. The AND gate outputs an AND logic signal after processing the chip select signal and ATD pulse, the filtered input terminal and delay unit both receive the AND logic signal from the AND gate; and send their signals to the comparator unit. The comparator unit performs a logic function on the AND logic signal and a delayed AND logic signal to produce the internal clock signal.Type: GrantFiled: November 9, 1995Date of Patent: October 15, 1996Assignee: The United States of America as represented by the Secretary of the Air ForceInventors: Christopher M. Durham, Michael K. Ciraula, Craig L. Stephen