Patents by Inventor Michael K. Dugan
Michael K. Dugan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11550719Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.Type: GrantFiled: March 3, 2021Date of Patent: January 10, 2023Assignee: Micron Technology, Inc.Inventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
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Publication number: 20210182195Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.Type: ApplicationFiled: March 3, 2021Publication date: June 17, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: TONY M. BREWER, J. MICHAEL ANDREWARTHA, WILLIAM D. O'LEARY, MICHAEL K. DUGAN
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Patent number: 10949347Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.Type: GrantFiled: July 18, 2018Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
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Publication number: 20180322054Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.Type: ApplicationFiled: July 18, 2018Publication date: November 8, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Tony M. Brewer, J. MICHAEL ANDREWARTHA, WILLIAM D. O'LEARY, MICHAEL K. DUGAN
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Patent number: 10061699Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.Type: GrantFiled: November 7, 2017Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
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Publication number: 20180060234Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.Type: ApplicationFiled: November 7, 2017Publication date: March 1, 2018Applicant: MICRON TECHNOLOGY, INC.Inventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
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Patent number: 9824010Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.Type: GrantFiled: September 1, 2016Date of Patent: November 21, 2017Assignee: Micron Technology, Inc.Inventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
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Publication number: 20160371185Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.Type: ApplicationFiled: September 1, 2016Publication date: December 22, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: TONY M. BREWER, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
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Patent number: 9449659Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.Type: GrantFiled: March 30, 2015Date of Patent: September 20, 2016Assignee: Micron Technology, Inc.Inventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
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Publication number: 20150206561Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.Type: ApplicationFiled: March 30, 2015Publication date: July 23, 2015Inventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
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Patent number: 9015399Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.Type: GrantFiled: August 5, 2008Date of Patent: April 21, 2015Assignee: Convey ComputerInventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
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Publication number: 20100036997Abstract: The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.Type: ApplicationFiled: August 5, 2008Publication date: February 11, 2010Applicant: Convey ComputerInventors: Tony M. Brewer, J. Michael Andrewartha, William D. O'Leary, Michael K. Dugan
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Publication number: 20080270708Abstract: A system and method are disclosed for achieving cache coherency in a multiprocessor computer system having a plurality of sockets with processing devices and memory controllers and a plurality of memory blocks. In at least some embodiments, the system includes a plurality of node controllers capable of being respectively coupled to the respective sockets of the multiprocessor computer, a plurality of caching devices respectively coupled to the respective node controllers, and a fabric coupling the respective node controllers, by which cache line request signals can be communicated between the respective node controllers. Cache coherency is achieved notwithstanding the cache line request signals communicated between the respective node controllers due at least in part to communications between the node controllers and the respective caching devices to which the node controllers are coupled.Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Inventors: Craig Warner, Bryan Hornung, Chris Michael Brueggen, Ryan L. Akkerman, Michael K. Dugan, Gary Gostin, Harvey Ray, Dan Robinson, Christopher Greer
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Patent number: 7366854Abstract: In an embodiment, a memory scheduler is provided to process memory requests. The memory scheduler may comprise: a plurality of arbitrators that each select memory requests according to age of the memory requests and whether resources are available for the memory requests; and a second-level arbitrator that selects, for an arbitration round, a series of memory requests made available by the plurality of arbitrators, wherein the second-level arbitrator begins the arbitration round by selecting a memory request from a least recently used (LRU) arbitrator of the plurality of arbitrators.Type: GrantFiled: May 8, 2003Date of Patent: April 29, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: John M. Wastlick, Michael K. Dugan
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Patent number: 6876657Abstract: Hardware interconnected around multiple packet forwarding engines prepends sequence numbers to packets going into multiple forwarding engines through parallel paths, After processing by the multiple forwarding engines, packets are reordered using queues and a packet ordering mechanism, such that the sequence numbers are put back into their original prepended order. Exception packets flowing through the forwarding engines do not follow a conventional fast path, but are processed off-line and emerge from the forwarding engines out of order relative to fast path packets. These exception packets are marked, such that after they exit the forwarding engines, they are ordered among themselves independent of conventional fast path packets. Viewed externally, all exception packets are ordered across all multiple forwarding engines independent of the fast path packets.Type: GrantFiled: December 14, 2000Date of Patent: April 5, 2005Assignee: Chiaro Networks, Ltd.Inventors: Tony M. Brewer, Michael K. Dugan, Jim Kleiner, Gregory S. Palmer, Paul F. Vogel
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Publication number: 20040225847Abstract: In an embodiment, a memory scheduler is provided to process memory requests. The memory scheduler may comprise: a plurality of arbitrators that each select memory requests according to age of the memory requests and whether resources are available for the memory requests; and a second-level arbitrator that selects, for an arbitration round, a series of memory requests made available by the plurality of arbitrators, wherein the second-level arbitrator begins the arbitration round by selecting a memory request from a least recently used (LRU) arbitrator of the plurality of arbitrators.Type: ApplicationFiled: May 8, 2003Publication date: November 11, 2004Inventors: John M. Wastlick, Michael K. Dugan
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Patent number: 6564306Abstract: An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.Type: GrantFiled: February 28, 2001Date of Patent: May 13, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Michael K Dugan, Gary B Gostin, Mark A Heap, Terry C Huang, Curtis R. McAllister, Henry Yu
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Publication number: 20010034815Abstract: An apparatus and method for performing speculative directory cache tag updates for read accesses to memory is herein disclosed. A control unit for performing tag updates is coupled between the memory controller and the memory bank in a multiprocessor system that employs a directory-based coherency protocol. The control unit transmits data read from the memory bank to the memory controller while calculating the updated tag that it then writes back to the memory bank. In this manner, the memory bank busy time and memory bus traffic are reduced thereby improving the overall performance of a memory access.Type: ApplicationFiled: February 28, 2001Publication date: October 25, 2001Inventors: Michael K. Dugan, Gary B. Gostin, Mark A. Heap, Terry C. Huang, Curtis R. McAllister, Henry Yu