Abstract: Embodiments of systems and methods disclosed herein include an embedded secret provisioning system that is based on a shared-derivative mechanism. Embodiments of this mechanism use a trusted third-party topology, but only a single instance of a public-private key exchange is required for initialization. Embodiments of the system and methods are secure and any of the derived secret keys are completely renewable in untrusted environments without any reliance on asymmetric cryptography. The derived secrets exhibit zero knowledge attributes and the associated zero knowledge proofs are open and available for review. Embodiments of systems and methods can be implemented in a wide range of previously-deployed devices as well as integrated into a variety of new designs using minimal roots-of-trust.

Abstract: Embodiments of systems and methods disclosed herein include an embedded secret provisioning system that is based on a shared-derivative mechanism. Embodiments of this mechanism use a trusted third-party topology, but only a single instance of a public-private key exchange is required for initialization. Embodiments of the system and methods are secure and any of the derived secret keys are completely renewable in untrusted environments without any reliance on asymmetric cryptography. The derived secrets exhibit zero knowledge attributes and the associated zero knowledge proofs are open and available for review. Embodiments of systems and methods can be implemented in a wide range of previously-deployed devices as well as integrated into a variety of new designs using minimal roots-of-trust.

Abstract: Embodiments of systems and methods disclosed herein include an embedded secret provisioning system that is based on a shared-derivative mechanism. Embodiments of this mechanism use a trusted third-party topology, but only a single instance of a public-private key exchange is required for initialization. Embodiments of the system and methods are secure and any of the derived secret keys are completely renewable in untrusted environments without any reliance on asymmetric cryptography. The derived secrets exhibit zero knowledge attributes and the associated zero knowledge proofs are open and available for review. Embodiments of systems and methods can be implemented in a wide range of previously-deployed devices as well as integrated into a variety of new designs using minimal roots-of-trust.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: A personal computer system displays digital content received from a content delivery server. The content delivery server provides the digital content as a result of being contacted by a server-contacting program stored on a disk drive in the computer and initiated by the drive firmware. The digital content can be any of a number of file types including AVI, MPEG, or MP3.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: A computer network connects a personal computer system to a content delivery system for delivering digital content to the personal computer. The personal computer comprises a disk drive which includes a network address for the content delivery system and a server-contacting program. The disk drive comprises firmware installed during manufacturing of the drive which initiates execution of the server-contacting program to enable the network connection and facilitate delivery of content to a large number of personal computers.

Abstract: An isochronous switched fabric network is disclosed comprising a plurality of interconnected switched nodes forming multiple dimensions, each switched node comprising an upstream port and a downstream port for each dimension, each upstream and downstream port comprising an input port and an output port. A discovery facility discovers a depth of each dimension, and discovers resources within each switched node. An addressing facility assigns a matrix address to each switched node, a resource reservation facility reserves resources within each switched node to establish a path through the switched fabric network for transmitting an isochronous data stream, and a scheduling facility schedules isochronous data transmitted through the switched fabric network.

Abstract: A content delivery server delivers digital content to a personal computer having a disk drive which stores a network address and server-contacting program for establishing a connection between the content delivery server and the personal computer. The content delivery system provides a variety of digital content including AVI, MPEG and MP3 format files to the personal computer and periodically refreshes the content according to user preferences.

Abstract: A disk drive is manufactured with a stored server-contacting program and a network address. Preferably, a protected area is provided for retaining the server-contacting program and the network address in the disk drive while it travels through a distribution channel to be installed in a user's personal computer system. The disk drive has firmware installed during manufacturing to initiate execution of the server-contacting program at an appropriate time, preferably when a selected condition has been met.

Abstract: A computer network is disclosed comprising a plurality of interconnected computer devices including a plurality of disk drives for storing network data, each disk drive comprising a head and a disk. The computer network comprises a plurality of interconnected nodes, and a reservation facility for reserving resources within the disk drives and the nodes to support a predetermined Quality-of-Service constraint with respect to data transmitted between the disk drives through the nodes of the computer network.

Abstract: A distributed method of establishing a path in a multi-dimensional computer network comprising a plurality of nodes for transmitting isochronous data from a source node to a destination node is disclosed. A request packet is injected into the network, the request packet specifying a request to transmit the isochronous data from one of a plurality of source nodes. The request packet is routed to at least one the plurality of source nodes, and the source node determines whether it has sufficient resources to support transmitting the isochronous data. If the source node comprises sufficient resources to support transmitting the isochronous data, the source node reserves resources within the source node to support transmitting the isochronous data, and transmits an ack packet from the source node to a first neighboring node. The first neighboring node determines whether it has sufficient resources to support transmitting the isochronous data.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: A switched node for use in a multi-dimensional switched fabric network is disclosed. The switched node comprises adapter circuitry connected to receive asynchronous and isochronous packets from an external entity. Each asynchronous packet comprises destination node routing information and data, and each isochronous packet comprises a path ID corresponding to a reserved path through the network, an arrival time parameter identifying a target arrival time of the isochronous packet into the switched node, and data. An asynchronous-to-isochronous converter converts the asynchronous packets into isochronous packets comprising the data from the asynchronous packets.

Abstract: A method for designing an integrated circuit includes selecting representations of integrated circuit components from a plurality of integrated circuit component representations, the representations suitable for being displayed on a display device. Connections are indicated between at least a portion of the selected representations of the integrated circuit components. An integrated circuit description is provided including the selected representations and the indicated connections between the representations, wherein the integrated circuit description includes data obtained from a database having characteristic data corresponding to the plurality of representations.

Abstract: This invention is directed to a method for processing file system service requests in a computer having an attached disk drive that in response to commands from the computer can write data to or read data from disk locations to reproduce stream data and non-stream data. The method comprises the steps of responding to a first file system service request by recording whether the first file system service request is for non-stream data or stream data, associating a first set of disk locations of the disk drive with the first file system service request, and preparing a first command that requires access to the first set of disk locations, the first command including control data categorizing the command as a non-stream access command or as a stream access command in response to the step of recording. The method includes transmitting the first command to the disk drive.

Abstract: A method for the loading and unloading of a FIFO in an isochronous transmission mechanism uses descriptor blocks which have both branch addresses and skip addresses. The method can recover from cycle loss by selectively resending or skipping a packet that should have been sent in the lost cycle. The method also works two cycles ahead of schedule, in an attempt to keep the FIFO loaded with all of the packets for two cycles of transmission. The FIFO is filled according to a DMA algorithm and drained according to a Link algorithm where the two algorithms are coordinated to communicate information about lost cycles and current demands or opportunities for transmission. If the Link algorithm detects a lost cycle, it communicates that to the DMA algorithm and the DMA algorithm seeks to compensate appropriately. These two algorithms describe mechanisms for the DMA and Link sides of an isochronous transmitter.

Abstract: The present invention is directed to improving the time with which information transfer signals can be generated in response to an initiating signal. Exemplary embodiments are described in the context of a small computer system interface, wherein enhanced operation is achieved by producing a response signal, such as an acknowledge signal, in close proximity to receipt of an initiating signal, such as a request signal. Further, exemplary embodiments achieve such improved operation without the use of complex circuitry; rather, relatively simple latching circuitry is provided in accordance with the present invention to substantially increase overall operating efficiency.

Abstract: The present invention is directed to providing a method and apparatus for improving the reliability of signal detection in signal lines used to receive information transfer signals such as the request and acknowledge signals of a small computer system interface, without degrading information transfer signals which are output from the small computer system interface and without inhibiting the use of both asynchronous and synchronous modes of information transfer. In accordance with exemplary embodiments, rather than using a filter to damp an incoming signal, a time-domain filter is used to determine when the incoming signal is expected to be valid. The time delay can, if desired, be programmed by the user so that the delay can be easily varied to account for specific signal conduits and peripheral devices. In accordance with exemplary embodiments, the information transfer signals can be received via the time-domain filter during an initial asynchronous mode of information transfer.

Abstract: The present invention is therefore directed to enhancing the efficiency with which input/output controllers execute operations in response to requests from another device, such as a main controller. In accordance with exemplary embodiments, a compact set of status information signals is communicated from an input/output controller to a main controller such that the main controller can provide error control (that is, monitor input/output controller operation) without the use of interrupts. As a result, the main controller can sequentially and continuously supply multiple commands of a transaction to the input/output controller without the use of a multiple hardware interrupts. System hardware can therefore be used more efficiently and input/output controller operation can be accelerated, thereby increasing system performance.