Abstract: A digital-to-analog converter (DAC). A DAC includes a plurality of DAC cells and a controller. The controller generates a control signal for driving the plurality of DAC cells for each clock cycle. The controller may generate the control signal to select a set of one or more DAC cells for an input code or for a standby mode of the DAC such that the selected set of one or more DAC cells to be active for the same input code or for the standby mode of the DAC change over time without affecting an output of the DAC more than a predetermined limit.

Abstract: Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.

Abstract: A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by ri bit positions for the i-th second digital control code, wherein ri is an integer smaller than N?1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes.

Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift ??. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters.

Abstract: Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (Mp) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (Mc) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (?gmf) comprising an input terminal and an output terminal.

Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift ??. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters.

Abstract: A digital-to-analog converter comprises a plurality of first digital-to-analog converter cells configured to generate a first analog signal based on first digital data, wherein the first digital-to-analog converter cells of the plurality of first digital-to-analog converter cells are coupled to a first output node for coupling to a first load. Further, the digital-to-analog converter comprises a plurality of second digital-to-analog converter cells configured to generate one or more second analog signals based on second digital data, wherein the second digital-to-analog converter cells of the plurality of second digital-to-analog converter cells are coupled to one or more second output nodes, and wherein the plurality of first digital-to-analog converter cells and the plurality of second digital-to-analog converter cells are coupled to a power supply node for coupling to a mutual power supply.

Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.