Patents by Inventor Michael Kochanowski
Michael Kochanowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7592702Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.Type: GrantFiled: July 31, 2006Date of Patent: September 22, 2009Assignee: Intel CorporationInventors: J. Shelton Lewis, Shawn Lloyd, Michael Kochanowski, John Oldendorf
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Publication number: 20080023840Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.Type: ApplicationFiled: July 31, 2006Publication date: January 31, 2008Inventors: J. S. Lewis, Shawn Lloyd, Michael Kochanowski, John Oldendorf
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Patent number: 7241147Abstract: A socket may receive both ball grid and land grid array packages. Thus, in some embodiments, the early package prototypes, without solder balls, may be packaged in the same socket design that is ultimately used for production devices using ball grid array packaging. Both land grid array and ball grid arrays may be self-centered on the socket in some embodiments. An S-shaped spring contact may be utilized to electrically connect to either solder balls or lands in a wiping action.Type: GrantFiled: April 12, 2004Date of Patent: July 10, 2007Assignee: Intel CorporationInventors: Shawn L. Lloyd, John G. Oldendorf, Michael Kochanowski, Scott A. Gilbert
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Publication number: 20060288567Abstract: A device includes a substrate. The substrate further includes a first major surface including a plurality of lands, and a second major surface. At least one component is attached to at least some of the plurality of pads on the first major surface. At least one sacrificial component is attached to the first major surface. The at least one component has a first height with respect to the first major surface, and the at least one sacrificial component has a second height with respect to the first major surface. The second height is greater than the first height. The sacrificial component includes a fuse.Type: ApplicationFiled: August 29, 2006Publication date: December 28, 2006Inventors: Shawn Lloyd, John Oldendorf, Michael Kochanowski, Scott Gilbert
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Patent number: 7124931Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.Type: GrantFiled: November 18, 2003Date of Patent: October 24, 2006Assignee: Intel CorporationInventors: J. Shelton Lewis, Shawn Lloyd, Michael Kochanowski, John Oldendorf
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Publication number: 20060216957Abstract: An integrated circuit (IC) package socket is provided with an array of single-piece socket contact pins arranged to connect an IC package to a circuit board. The single-piece contact pin is supported at a middle portion of the contact pin and includes two acutely angled bends that allow the two ends of the contact pin to independently resiliently engage the package lands of the IC package and the contact pads of the circuit board. The contact pins are further shaped and arranged to laterally swipe the package lands and contact pads during engagement to scrape away or penetrate through any oxide or other contaminant buildup.Type: ApplicationFiled: March 25, 2005Publication date: September 28, 2006Inventors: Shawn Lloyd, John Oldendorf, J. Lewis, Michael Kochanowski
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Patent number: 7104803Abstract: An integrated circuit (IC) package socket is provided with an array of single-piece socket contact pins arranged to connect an IC package to a circuit board. The single-piece contact pin is supported at a middle portion of the contact pin and includes two acutely angled bends that allow the two ends of the contact pin to independently resiliently engage the package lands of the IC package and the contact pads of the circuit board. The contact pins are further shaped and arranged to laterally swipe the package lands and contact pads during engagement to scrape away or penetrate through any oxide or other contaminant buildup.Type: GrantFiled: March 25, 2005Date of Patent: September 12, 2006Assignee: Intel CorporationInventors: Shawn L. Lloyd, John G. Oldendorf, J. Shelton Lewis, Michael Kochanowski
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Patent number: 7098534Abstract: A device includes a substrate. The substrate further includes a first major surface including a plurality of lands, and a second major surface. At least one component is attached to at least some of the plurality of pads on the first major surface. At least one sacrificial component is attached to the first major surface. The at least one component has a first height with respect to the first major surface, and the at least one sacrificial component has a second height with respect to the first major surface. The second height is greater than the first height. The sacrificial component includes a fuse.Type: GrantFiled: March 31, 2004Date of Patent: August 29, 2006Assignee: Intel CorporationInventors: Shawn L. Lloyd, John G. Oldendorf, Michael Kochanowski, Scott Gilbert
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Publication number: 20050227509Abstract: A socket may receive both ball grid and land grid array packages. Thus, in some embodiments, the early package prototypes, without solder balls, may be packaged in the same socket design that is ultimately used for production devices using ball grid array packaging. Both land grid array and ball grid arrays may be self-centered on the socket in some embodiments. An S-shaped spring contact may be utilized to electrically connect to either solder balls or lands in a wiping action.Type: ApplicationFiled: April 12, 2004Publication date: October 13, 2005Inventors: Shawn Lloyd, John Oldendorf, Michael Kochanowski, Scott Gilbert
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Publication number: 20050218516Abstract: A device includes a substrate. The substrate further includes a first major surface including a plurality of lands, and a second major surface. At least one component is attached to at least some of the plurality of pads on the first major surface. At least one sacrificial component is attached to the first major surface. The at least one component has a first height with respect to the first major surface, and the at least one sacrificial component has a second height with respect to the first major surface. The second height is greater than the first height. The sacrificial component includes a fuse.Type: ApplicationFiled: March 31, 2004Publication date: October 6, 2005Inventors: Shawn Lloyd, John Oldendorf, Michael Kochanowski, Scott Gilbert
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Publication number: 20050103826Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.Type: ApplicationFiled: November 18, 2003Publication date: May 19, 2005Inventors: J.S. Lewis, Shawn Lloyd, Michael Kochanowski, John Oldendorf
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Patent number: 6566611Abstract: A substrate, such as a printed circuit board (PCB), has pairs of pads to which terminals of electronic components, such as capacitors, can be mounted. The pads have perimeters, for example, in the shape of rectangles, circles, or ovals. In one embodiment, to reduce asymmetrical, lateral, surface-tension forces that can cause the components to tombstone due to uneven heating of solder fillets on the pads during solder reflow, the edge of the perimeter of each pad opposite the inter-pad region contains one or more notches or indentations. Also described are an electronic assembly, an electronic system, and various methods of fabrication.Type: GrantFiled: September 26, 2001Date of Patent: May 20, 2003Assignee: Intel CorporationInventors: Michael Kochanowski, Mandy G. Terhaar, Cheryl M. Floyde, George Hsieh
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Publication number: 20030056975Abstract: A substrate, such as a printed circuit board (PCB), has pairs of pads to which terminals of electronic components, such as capacitors, can be mounted. The pads have perimeters, for example, in the shape of rectangles, circles, or ovals. In one embodiment, to reduce asymmetrical, lateral, surface-tension forces that can cause the components to tombstone due to uneven heating of solder fillets on the pads during solder reflow, the edge of the perimeter of each pad opposite the inter-pad region contains one or more notches or indentations. Also described are an electronic assembly, an electronic system, and various methods of fabrication.Type: ApplicationFiled: September 26, 2001Publication date: March 27, 2003Applicant: Intel CorporationInventors: Michael Kochanowski, Mandy G. Terhaar, Cheryl M. Floyde, George Hsieh