Patents by Inventor Michael Kochanowski

Michael Kochanowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7592702
    Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: September 22, 2009
    Assignee: Intel Corporation
    Inventors: J. Shelton Lewis, Shawn Lloyd, Michael Kochanowski, John Oldendorf
  • Publication number: 20080023840
    Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Inventors: J. S. Lewis, Shawn Lloyd, Michael Kochanowski, John Oldendorf
  • Patent number: 7241147
    Abstract: A socket may receive both ball grid and land grid array packages. Thus, in some embodiments, the early package prototypes, without solder balls, may be packaged in the same socket design that is ultimately used for production devices using ball grid array packaging. Both land grid array and ball grid arrays may be self-centered on the socket in some embodiments. An S-shaped spring contact may be utilized to electrically connect to either solder balls or lands in a wiping action.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: July 10, 2007
    Assignee: Intel Corporation
    Inventors: Shawn L. Lloyd, John G. Oldendorf, Michael Kochanowski, Scott A. Gilbert
  • Publication number: 20060288567
    Abstract: A device includes a substrate. The substrate further includes a first major surface including a plurality of lands, and a second major surface. At least one component is attached to at least some of the plurality of pads on the first major surface. At least one sacrificial component is attached to the first major surface. The at least one component has a first height with respect to the first major surface, and the at least one sacrificial component has a second height with respect to the first major surface. The second height is greater than the first height. The sacrificial component includes a fuse.
    Type: Application
    Filed: August 29, 2006
    Publication date: December 28, 2006
    Inventors: Shawn Lloyd, John Oldendorf, Michael Kochanowski, Scott Gilbert
  • Patent number: 7124931
    Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: J. Shelton Lewis, Shawn Lloyd, Michael Kochanowski, John Oldendorf
  • Publication number: 20060216957
    Abstract: An integrated circuit (IC) package socket is provided with an array of single-piece socket contact pins arranged to connect an IC package to a circuit board. The single-piece contact pin is supported at a middle portion of the contact pin and includes two acutely angled bends that allow the two ends of the contact pin to independently resiliently engage the package lands of the IC package and the contact pads of the circuit board. The contact pins are further shaped and arranged to laterally swipe the package lands and contact pads during engagement to scrape away or penetrate through any oxide or other contaminant buildup.
    Type: Application
    Filed: March 25, 2005
    Publication date: September 28, 2006
    Inventors: Shawn Lloyd, John Oldendorf, J. Lewis, Michael Kochanowski
  • Patent number: 7104803
    Abstract: An integrated circuit (IC) package socket is provided with an array of single-piece socket contact pins arranged to connect an IC package to a circuit board. The single-piece contact pin is supported at a middle portion of the contact pin and includes two acutely angled bends that allow the two ends of the contact pin to independently resiliently engage the package lands of the IC package and the contact pads of the circuit board. The contact pins are further shaped and arranged to laterally swipe the package lands and contact pads during engagement to scrape away or penetrate through any oxide or other contaminant buildup.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventors: Shawn L. Lloyd, John G. Oldendorf, J. Shelton Lewis, Michael Kochanowski
  • Patent number: 7098534
    Abstract: A device includes a substrate. The substrate further includes a first major surface including a plurality of lands, and a second major surface. At least one component is attached to at least some of the plurality of pads on the first major surface. At least one sacrificial component is attached to the first major surface. The at least one component has a first height with respect to the first major surface, and the at least one sacrificial component has a second height with respect to the first major surface. The second height is greater than the first height. The sacrificial component includes a fuse.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 29, 2006
    Assignee: Intel Corporation
    Inventors: Shawn L. Lloyd, John G. Oldendorf, Michael Kochanowski, Scott Gilbert
  • Publication number: 20050227509
    Abstract: A socket may receive both ball grid and land grid array packages. Thus, in some embodiments, the early package prototypes, without solder balls, may be packaged in the same socket design that is ultimately used for production devices using ball grid array packaging. Both land grid array and ball grid arrays may be self-centered on the socket in some embodiments. An S-shaped spring contact may be utilized to electrically connect to either solder balls or lands in a wiping action.
    Type: Application
    Filed: April 12, 2004
    Publication date: October 13, 2005
    Inventors: Shawn Lloyd, John Oldendorf, Michael Kochanowski, Scott Gilbert
  • Publication number: 20050218516
    Abstract: A device includes a substrate. The substrate further includes a first major surface including a plurality of lands, and a second major surface. At least one component is attached to at least some of the plurality of pads on the first major surface. At least one sacrificial component is attached to the first major surface. The at least one component has a first height with respect to the first major surface, and the at least one sacrificial component has a second height with respect to the first major surface. The second height is greater than the first height. The sacrificial component includes a fuse.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Inventors: Shawn Lloyd, John Oldendorf, Michael Kochanowski, Scott Gilbert
  • Publication number: 20050103826
    Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.
    Type: Application
    Filed: November 18, 2003
    Publication date: May 19, 2005
    Inventors: J.S. Lewis, Shawn Lloyd, Michael Kochanowski, John Oldendorf
  • Patent number: 6566611
    Abstract: A substrate, such as a printed circuit board (PCB), has pairs of pads to which terminals of electronic components, such as capacitors, can be mounted. The pads have perimeters, for example, in the shape of rectangles, circles, or ovals. In one embodiment, to reduce asymmetrical, lateral, surface-tension forces that can cause the components to tombstone due to uneven heating of solder fillets on the pads during solder reflow, the edge of the perimeter of each pad opposite the inter-pad region contains one or more notches or indentations. Also described are an electronic assembly, an electronic system, and various methods of fabrication.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: May 20, 2003
    Assignee: Intel Corporation
    Inventors: Michael Kochanowski, Mandy G. Terhaar, Cheryl M. Floyde, George Hsieh
  • Publication number: 20030056975
    Abstract: A substrate, such as a printed circuit board (PCB), has pairs of pads to which terminals of electronic components, such as capacitors, can be mounted. The pads have perimeters, for example, in the shape of rectangles, circles, or ovals. In one embodiment, to reduce asymmetrical, lateral, surface-tension forces that can cause the components to tombstone due to uneven heating of solder fillets on the pads during solder reflow, the edge of the perimeter of each pad opposite the inter-pad region contains one or more notches or indentations. Also described are an electronic assembly, an electronic system, and various methods of fabrication.
    Type: Application
    Filed: September 26, 2001
    Publication date: March 27, 2003
    Applicant: Intel Corporation
    Inventors: Michael Kochanowski, Mandy G. Terhaar, Cheryl M. Floyde, George Hsieh