Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

Abstract: An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

Abstract: According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.

Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

Abstract: According to one embodiment of the present invention, a temperature sensor is provided, including a first electrode, a second electrode, a nanoporous material disposed between the first electrode and the second electrode, and a diffusion material which is located outside the nanoporous material that is capable of diffusion into the nanoporous material. The amount of diffusion material diffusing into the nanoporous material is dependent on the temperature to which the temperature sensor is exposed. The resistance of the nanoporous material is dependent on the amount of diffusion material diffusing into the nanoporous material.

Abstract: An integrated circuit is described, including a memory element including a first carbon layer rich in a first carbon material and a second carbon layer rich in a second carbon material. The memory element stores information by reversibly forming a conductive channel in the second carbon layer, wherein the conductive channel includes the first carbon material.

Abstract: An electric device protection circuit comprises at least one conductive bridging unit which electrically connects a terminal of the electric device to a protection node set to a protection potential, the protection potential being chosen such that the conductive bridging unit switches from a resistive state to a conductive state in case that the voltage or current at the terminal exceeds a predetermined threshold value.

Abstract: According to an embodiment, an integrated circuit including a plurality of resistance changing memory cells is disclosed. Each memory cell includes a first electrode, a second electrode and resistance changing memory element arranged between the first electrode and the second electrode. A front surface area of an end section of the first electrode that faces the resistance changing memory element is smaller than a front surface area of an end section of the second electrode that faces the resistance changing memory element.

Abstract: An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

Abstract: A tunable resistor includes a resistor input terminal, a resistor output terminal, and at least one current path connected between the resistor input terminal and the resistor output terminal. The at least one current path runs through at least one memory cell of an arrangement of programmable microelectronic memory cells. A resistance adjuster adjusts the current path resistances of the current paths by programming the memory states of corresponding memory cells or which activates/deactivates current paths such that the overall resistance between the resistor input terminal and the resistor output terminal is set to a predetermined resistance target value.

Abstract: Provided is a resistive memory arrangement having a cell array structured in rows and columns and having resistive memory cells connected to a drive element for driving. Each drive element is jointly connected to n cell resistors forming a memory cell, the cell resistors being CBRAM resistance elements, in particular, and also to a writing, reading and erasing method for a resistive memory arrangement realized with CBRAM resistance elements.

Abstract: According to one embodiment of the present invention, a method of testing a memory device including a memory cell array is provided, the method including: dividing the memory cell array into a plurality of memory cell array subunits, each memory cell array subunit including a plurality of resistivity changing memory cells; simultaneously testing all resistivity changing memory cells of a memory cell array subunit using a common testing signal; and repeating the testing for all further memory cell array subunits.

Abstract: A method which makes it possible to define in a patterning layer openings having a first dimension that is substantially less than the feature size that can be obtained lithographically includes applying a sacrificial layer made of a material that is different from that of the patterning layer in a predetermined layer thickness on the patterning layer. Afterward, a photoresist layer is applied on the surface of the sacrificial layer, and an opening having a second dimension is defined lithographically in the photoresist layer. Afterward, an etching angle is set in a manner dependent on the layer thickness of the sacrificial layer and also the first and second dimensions, and the sacrificial layer is etched at the etching angle set. Afterward, the patterning layer is etched, the sacrificial layer is removed and a filling material is introduced into the opening produced in the patterning layer.

Abstract: A method of fabricating a memory cell including a solid electrolyte layer doped with metallic material and an electrode layer arranged above the solid electrolyte layer. The method includes doping a solid electrolyte layer with metallic material and forming an electrode layer above the solid electrolyte layer, wherein doping the solid electrolyte layer is carried out before forming the electrode layer.

Abstract: According to one embodiment of the present invention, a temperature sensor is provided, including a first electrode, a second electrode, a nanoporous material disposed between the first electrode and the second electrode, and a diffusion material which is located outside the nanoporous material that is capable of diffusion into the nanoporous material. The amount of diffusion material diffusing into the nanoporous material is dependent on the temperature to which the temperature sensor is exposed. The resistance of the nanoporous material is dependent on the amount of diffusion material diffusing into the nanoporous material.

Abstract: The invention relates to a system, a memory component and a process for operating a memory cell, which includes an active material, which can be changed into a more or less conductive state by an appropriate switching process, whereby the process including (a) bringing the memory cell into the more or less conductive state and evaluating the state of the memory cell after it has been changed into the more or less conductive state.

Abstract: According to one embodiment of the present invention, an integrated circuit is provided which includes a plurality of resistivity changing cells. At least two resistance ranges are assigned to each resistivity changing cell, each resistance range defining a possible state of the resistivity changing cell. The integrated circuit is operable in a cell initializing mode in which initializing signals are applied to the resistivity changing cells. The strengths and durations of the initializing signals are chosen such that the resistance of each resistivity changing cell is shifted into one of the resistance ranges assigned to the resistivity changing cell.

Abstract: According to one embodiment of the present invention, an integrated circuit includes a plurality of memory cells, the integrated circuit being operable in a memory cell testing mode in which testing signals are applied to the memory cells, wherein the strengths and durations of the testing signals at least partly differ from the strengths and durations of programming signals or sensing signals used for programming and sensing memory states of the memory cells.

Abstract: Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.