Abstract: A memory cache (46) has a plurality of tag arrays (20, 22, 24, 26), a plurality of comparators (38, 40, 42, 44), a plurality a data arrays (12, 14, 16, 18), and a plurality of sense amplifiers (48, 50, 52, 54). The memory cache executes a parallel tag and data array access but does not enable any sense amplifier until a comparator indicates a cache hit. Consequently, the memory cache is suitable for use where power consumption and speed are equally important design constraints.

Abstract: A clock signal (202) is received, wherein the rising edge of the clock signal (202) controls an operation of a memory cell (224) of a memory circuit (200). Address information (204) is received and predecoded prior to the rising edge of the clock signal (202) to produce a row select signal (210). A control signal (201), which is received prior to the rising edge of the clock signal, determines whether the operation is a read operation or a write operation. If the operation is a write operation, new data information (218) is received a data delay after the rising edge of the clock signal (202); the row select signal (210) is delayed such that the memory cell (224) is selected at least a data delay after the rising edge of the clock signal (202); and the new data information (218) is written to the memory cell (224).