Abstract: A processing system allocates memory to co-locate input and output operands for operations for processing in memory (PIM) execution in the same PIM-local memory while exploiting row-buffer locality and complying with conventional memory abstraction. The processing system identifies as “super rows” virtual rows that span all the banks of a memory device. Each super row has a different bank-interleaving pattern, referred to as a “color”. A group of contiguous super rows that has the same PIM-interleaving pattern is referred to as a “color group”. The processing system assigns memory addresses to each operand (e.g., vector) of an operation for PIM execution to a super row having a different color within the same color group to co-locate the operands for each PIM execution unit and uses address hashing to alternate between banks assigned to elements of a first operand and elements of a second operand of the operation.

Abstract: An apparatus that manages multi-process execution in a processing-in-memory (“PIM”) device includes a gatekeeper configured to: receive an identification of one or more registered PIM processes; receive, from a process, a memory request that includes a PIM command; if the requesting process is a registered PIM process and another registered PIM process is active on the PIM device, perform a context switch of PIM state between the registered PIM processes; and issue the PIM command of the requesting process to the PIM device.

Abstract: Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

Abstract: Components for valve treatment systems are disclosed. Valve treatment systems can include a delivery system for an implantable device. The delivery system can include one or more of clasp control components slidably disposed on a catheter handle, a control element for opening and closing the implantable device, a catheter assembly with features to reduce friction with another catheter assembly, grips for attaching catheter assemblies to clamps, catheter assemblies with features that stiffen or provide variable stiffness, and catheter assemblies with one or more steering control lumens incorporated into a reinforcement layer.

Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.

Abstract: An apparatus that manages multi-process execution in a processing-in-memory (“PIM”) device includes a gatekeeper configured to: receive an identification of one or more registered PIM processes; receive, from a process, a memory request that includes a PIM command; if the requesting process is a registered PIM process and another registered PIM process is active on the PIM device, perform a context switch of PIM state between the registered PIM processes; and issue the PIM command of the requesting process to the PIM device.

Abstract: Process isolation for a PIM device through exclusive locking includes receiving, from a process, a call requesting ownership of a PIM device. The request includes one or more PIM configuration parameters. The exclusive locking technique also includes granting the process ownership of the PIM device responsive to determining that ownership is available. The PIM device is configured according to the PIM configuration parameters.

Abstract: Process isolation for a PIM device includes: receiving, from a process, a call to allocate a virtual address space where the process stores a PIM configuration context; allocating the virtual address space including mapping a physical address space including PIM device configuration registers to the virtual address space only if the physical address space is not mapped to another process's virtual address space; and programming the PIM device configuration space according to the configuration context. When a PIM command is executed, a translation mechanism determines whether there is a valid mapping of a virtual address of the PIM command to a physical address of a PIM resource, such as a LIS entry. If a valid mapping exists, the translation is completed and the resource is accessed, but if there is not a valid mapping, the translation fails and the process is blocked from accessing the PIM resource.

Abstract: A method of training a neural network includes, at a local computing node, receiving remote parameters from a set of one or more remote computing nodes, initiating execution of a forward pass in a local neural network in the local computing node to determine a final output based on the remote parameters, initiating execution of a backward pass in the local neural network to determine updated parameters for the local neural network, and prior to completion of the backward pass, transmitting a subset of the updated parameters to the set of remote computing nodes.

Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.

Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.

Abstract: A processing system includes a processing unit and a memory device. The memory device includes a processing-in-memory (PIM) module that performs processing operations on behalf of the processing unit. An instruction set architecture (ISA) of the PIM module has fewer instructions than an ISA of the processing unit. Instructions received from the processing unit are translated such that processing resources of the PIM module are virtualized. As a result, the PIM module concurrently performs processing operations for multiple threads or applications of the processing unit.

Abstract: One or more processing units, such as a graphics processing unit (GPU), execute an application. A resource manager selectively allocates a first memory portion or a second memory portion to the processing units based on memory access characteristics. The first memory portion has a first latency that is lower that a second latency of the second memory portion. In some cases, the memory access characteristics indicate a latency sensitivity. In some cases, hints included in corresponding program code are used to determine the memory access characteristics. The memory access characteristics can also be determined by monitoring memory access requests, measuring a cache miss rate or a row buffer miss rate for the monitored memory access requests, and determining the memory access characteristics based on the cache miss rate or the row buffer miss rate.

Abstract: An execution environment in a computer system provides dynamic data and compute resources elasticity for user code to improve execution efficiency. The execution environment translates the user code into a runtime agnostic representation with a set of tasks. For each task, the execution environment determines a level of concurrency for executing the task based on the size of the set of input data for the task, the amount of compute resources available at the time of invocation of the task, and any context-sensitive heuristics provided by the user code.

Abstract: An execution environment in a computer system supports a declarative programming model where user code is written with a query syntax in a native programming language to express inherent parallelism in terms of data flow. The execution environment translates queries in the user code into a runtime agnostic representation and dynamically selects an execution runtime for executing the runtime agnostic representation.

Abstract: Functionality is described for providing a compiled program that can be executed in a parallel and a distributed manner by any selected runtime environment. The functionality includes a compiler module for producing the compiled program based on a dataflow representation of a program (i.e., a dataflow-expressed program). The dataflow-expressed program, in turn, includes a plurality of tasks that are connected together in a manner specified by a graph (such as a directed acyclic graph). The compiler module also involves performing static type-checking on the dataflow-expressed program to identify the presence of any mismatch errors in the dataflow-expressed program. By virtue of this approach, the above-described functionality can identify any errors in constructing the graph prior to its instantiation and execution in a runtime environment.

Abstract: A method of training a neural network includes, at a local computing node, receiving remote parameters from a set of one or more remote computing nodes, initiating execution of a forward pass in a local neural network in the local computing node to determine a final output based on the remote parameters, initiating execution of a backward pass in the local neural network to determine updated parameters for the local neural network, and prior to completion of the backward pass, transmitting a subset of the updated parameters to the set of remote computing nodes.

Abstract: Functionality is described for providing a compiled program that can be executed in a parallel and a distributed manner by any selected runtime environment. The functionality includes a compiler module for producing the compiled program based on a dataflow representation of a program (i.e., a dataflow-expressed program). The dataflow-expressed program, in turn, includes a plurality of tasks that are connected together in a manner specified by a graph (such as a directed acyclic graph). The compiler module also involves performing static type-checking on the dataflow-expressed program to identify the presence of any mismatch errors in the dataflow-expressed program. By virtue of this approach, the above-described functionality can identify any errors in constructing the graph prior to its instantiation and execution in a runtime environment.

Abstract: Functionality is described for providing a compiled program that can be executed in a parallel and a distributed manner by any selected runtime environment. The functionality includes a compiler module for producing the compiled program based on a dataflow representation of a program (i.e., a dataflow-expressed program). The dataflow-expressed program, in turn, includes a plurality of tasks that are connected together in a manner specified by a graph (such as a directed acyclic graph). The compiler module also involves performing static type-checking on the dataflow-expressed program to identify the presence of any mismatch errors in the dataflow-expressed program. By virtue of this approach, the above-described functionality can identify any errors in constructing the graph prior to its instantiation and execution in a runtime environment.

Abstract: An execution environment in a computer system supports a declarative programming model where user code is written with a query syntax in a native programming language to express inherent parallelism in terms of data flow. The execution environment translates queries in the user code into a runtime agnostic representation and dynamically selects an execution runtime for executing the runtime agnostic representation.