Patents by Inventor Michael L. McSwiney

Michael L. McSwiney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11848229
    Abstract: Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups, at least one functional group selected from amino groups, hydroxyl groups, ether linkages or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: December 19, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Michael L. McSwiney, Bhaskar Jyoti Bhuyan, Mark Saly, Drew Phillips, Aaron Dangerfield, David Thompson, Kevin Kashefi, Xiangjin Xie
  • Publication number: 20230317516
    Abstract: Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a metal-carbonyl containing precursor to form a self-assembled monolayer (SAM) on metallic surfaces.
    Type: Application
    Filed: July 14, 2022
    Publication date: October 5, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Muthukumar Kaliappan, Michael Haverty, Bhaskar Jyoti Bhuyan, Mark Saly, Aaron Dangerfield, Michael L. McSwiney, Feng Q. Liu, Xiangjin Xie
  • Publication number: 20230132200
    Abstract: Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups selected from alkene, alkyne, ketone, hydroxyl, aldehyde, or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.
    Type: Application
    Filed: October 21, 2022
    Publication date: April 27, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Michael L. McSwiney, Bhaskar Jyoti Bhuyan, Mark Saly, Drew Phillips, Aaron Dangerfield, David Thompson, Kevin Kashefi, Xiangjin Xie
  • Publication number: 20230126055
    Abstract: Methods for selectively depositing on metallic surfaces are disclosed. Some embodiments of the disclosure utilize a hydrocarbon having at least two functional groups, at least one functional group selected from amino groups, hydroxyl groups, ether linkages or combinations thereof to form a self-assembled monolayer (SAM) on metallic surfaces.
    Type: Application
    Filed: October 21, 2022
    Publication date: April 27, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Michael L. McSwiney, Bhaskar Jyoti Bhuyan, Mark Saly, Drew Phillips, Aaron Dangerfield, David Thompson, Kevin Kashefi, Xiangjin Xie
  • Patent number: 10658487
    Abstract: Embodiments of the present disclosure describe semiconductor devices with ruthenium phosphorus thin films and further describe the processes to deposit the thin films. The thin films may be deposited in a gate stack of a transistor device or in an interconnect structure. The processes to deposit the films may include chemical vapor deposition and may include ruthenium precursors. The precursors may contain phosphorus. A co-reactant may be used during deposition. A co-reactant may include a phosphorus based compound. A gate material may be deposited on the film in a gate stack. The ruthenium phosphorus film may be a metal diffusion barrier and an adhesion layer, and the film may be a work function metal for some embodiments. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Scott B. Clendenning, Han Wui Then, John J. Plombon, Michael L. McSwiney
  • Publication number: 20200066645
    Abstract: Embodiments of the invention include a microelectronic device that includes a substrate having a layer of dielectric material that includes a feature with a depression, a Tungsten containing barrier liner layer formed in the depression of the feature, and a Cobalt conductive layer deposited on the Tungsten containing barrier liner layer in the depression of the feature. The Tungsten containing barrier liner layer provides adhesion for the Cobalt conductive layer.
    Type: Application
    Filed: September 30, 2016
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Jason A. FARMER, Jeffrey S. LEIB, Michael L. MCSWINEY, Harsono S. SIMKA, Daniel B. BERGSTROM
  • Publication number: 20190252511
    Abstract: Embodiments of the present disclosure describe semiconductor devices with ruthenium phosphorus thin films and further describe the processes to deposit the thin films. The thin films may be deposited in a gate stack of a transistor device or in an interconnect structure. The processes to deposit the films may include chemical vapor deposition and may include ruthenium precursors. The precursors may contain phosphorus. A co-reactant may be used during deposition. A co-reactant may include a phosphorus based compound. A gate material may be deposited on the film in a gate stack. The ruthenium phosphorus film may be a metal diffusion barrier and an adhesion layer, and the film may be a work function metal for some embodiments. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 9, 2015
    Publication date: August 15, 2019
    Inventors: Scott B. CLENDENNING, Han Wui THEN, John J. PLOMBON, Michael L. MCSWINEY
  • Patent number: 8633463
    Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times, in some embodiments. In one embodiment, two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: January 21, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jong-Won Lee, Kuo-Wei Chang, Michael L. McSwiney
  • Publication number: 20130299767
    Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times, in some embodiments. In one embodiment, two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.
    Type: Application
    Filed: July 18, 2013
    Publication date: November 14, 2013
    Inventors: Jong-Won Lee, Kuo-Wei Chang, Michael L. McSwiney
  • Patent number: 8501523
    Abstract: Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times, in some embodiments. In one embodiment, two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jong-Won Lee, Kuo-Wei Chang, Michael L. McSwiney
  • Patent number: 8227335
    Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Valery M. Dubin, Michael L. McSwiney, Peter Moon
  • Publication number: 20120091542
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include introducing a first metal source, a second metal source and an oxygen source into a chamber and then forming a ternary oxide film comprising a first percentage of the first metal, a second percentage of the second metal, and a third percentage of oxygen.
    Type: Application
    Filed: December 19, 2011
    Publication date: April 19, 2012
    Inventors: Mark R. Brazier, Matthew V. Metz, Michael L. McSwiney, Markus Kuhn, Michael L. Hattendorf
  • Patent number: 8003293
    Abstract: A deliberately engineered placement and size constraint (molecular weight distribution) of photoacid generators, solubility switches, photoimageable species, and quenchers forms individual pixels within a photoresist. Upon irradiation, a self-contained reaction occurs within each of the individual pixels that were irradiated to pattern the photoresist. These pixels may take on a variety of forms including a polymer chain, a bulky cluster, a micelle, or a micelle formed of several polymer chains. Furthermore, these pixels may be designed to self-assemble onto the substrate on which the photoresist is applied.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: August 23, 2011
    Assignee: Intel Corporation
    Inventors: Robert P. Meagley, Michael D. Goodner, Bob E. Leet, Michael L. McSwiney
  • Patent number: 7704858
    Abstract: A method for forming a nickel silicide layer on a MOS device with a low carbon content comprises providing a substrate within an ALD reactor and performing an ALD process cycle to form a nickel layer on the substrate, wherein the ALD process cycle comprises pulsing a nickel precursor into the reactor, purging the reactor after the nickel precursor, pulsing a mixture of hydrogen and silane into the reactor, and purging the reactor after the hydrogen and silane pulse. The ALD process cycle can be repeated until the nickel layer reaches a desired thickness. The silane used in the ALD process functions as a getterer for the advantageous carbon, resulting in a nickel layer that has a low carbon content. The nickel layer may then be annealed to form a nickel silicide layer with a low carbon content.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: April 27, 2010
    Assignee: Intel Corporation
    Inventors: Michael L. McSwiney, Matthew V. Metz
  • Publication number: 20090096025
    Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.
    Type: Application
    Filed: December 15, 2008
    Publication date: April 16, 2009
    Inventors: Peter G. Tolchinsky, Martin D. Giles, Michael L. McSwiney, Mohamad Shaheen, Irwin Yablok
  • Publication number: 20090087623
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include introducing a first metal source, a second metal source and an oxygen source into a chamber and then forming a ternary oxide film comprising a first percentage of the first metal, a second percentage of the second metal, and a third percentage of oxygen.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventors: Mark R. Brazier, Matthew V. Metz, Michael L. McSwiney, Markus Kuhn, Michael L. Hattendorf
  • Patent number: 7473614
    Abstract: Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: January 6, 2009
    Assignee: Intel Corporation
    Inventors: Peter G. Tolchinsky, Martin D. Giles, Michael L. McSwiney, Mohamad Shaheen, Irwin Yablok
  • Patent number: 7470450
    Abstract: A silicon nitride film may be deposited on a work piece using conventional deposition techniques and a selected source for use as a silicon precursor. A nitrogen precursor may also be selected for film deposition. Using the selected precursor(s), the temperature for deposition may be 500° C., or less.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: December 30, 2008
    Assignee: Intel Corporation
    Inventors: Michael L. McSwiney, Mansour Moinpour, Michael D. Goodner
  • Patent number: 7459392
    Abstract: A barrier and seed layer for a semiconductor damascene process is described. The seed layer is formed from a noble metal with an intermediate region between the barrier and noble metal layers to prevent oxidation of the barrier layer.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: December 2, 2008
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Juan E. Dominguez, Michael L. McSwiney
  • Patent number: 7452728
    Abstract: Methods and systems for the concentration and removal of metal ions from aqueous solutions are described, comprising treating the aqueous solutions with photoswitchable ionophores.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: November 18, 2008
    Assignee: Intel Corporation
    Inventors: Bob E. Leet, Robert P. Meagley, Michael D. Goodner, Michael L. McSwiney