Patents by Inventor Michael L. Rieger
Michael L. Rieger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9209129Abstract: Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.Type: GrantFiled: July 10, 2014Date of Patent: December 8, 2015Assignee: Synopsys, Inc.Inventors: Michael L. Rieger, Victor Moroz
-
Publication number: 20150103392Abstract: In one embodiment, an apparatus includes a retroreflector pixel that includes multiple retroreflector sub-pixels. Each retroreflector sub-pixel includes a reflective surface configured to reflect incident light. Each retroreflector sub-pixel also includes a filter element configured to filter out from the incident light an electrically-controllable amount of light over a particular wavelength range. The filter element may utilize an electrophoretic technique based on charged particles, an electrowetting technique based on a dyed fluid, or an evanescent-wave coupling technique. The apparatus may include a controller communicably coupled to the retroreflector pixel and operable to control the filter element of each retroreflector sub-pixel.Type: ApplicationFiled: December 13, 2013Publication date: April 16, 2015Applicant: SYNOPSYS, INC.Inventor: Michael L. Rieger
-
Publication number: 20140367855Abstract: Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.Type: ApplicationFiled: July 10, 2014Publication date: December 18, 2014Inventors: Michael L. Rieger, Victor Moroz
-
Patent number: 8893061Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage.Type: GrantFiled: March 3, 2014Date of Patent: November 18, 2014Assignee: Synopsys, Inc.Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
-
Patent number: 8813012Abstract: Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.Type: GrantFiled: July 16, 2012Date of Patent: August 19, 2014Assignee: Synopsys, Inc.Inventors: Michael L. Rieger, Victor Moroz
-
Publication number: 20140189616Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage.Type: ApplicationFiled: March 3, 2014Publication date: July 3, 2014Applicant: Synopsys, Inc.Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
-
Patent number: 8667429Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.Type: GrantFiled: November 26, 2012Date of Patent: March 4, 2014Assignee: Synopsys, Inc.Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
-
Publication number: 20140015135Abstract: Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.Type: ApplicationFiled: July 16, 2012Publication date: January 16, 2014Applicant: SYNOPSYS, INC.Inventors: Michael L. Rieger, Victor Moroz
-
Patent number: 8490032Abstract: Techniques and systems for converting a non-bandlimited pattern layout into a band-limited pattern image are described. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout.Type: GrantFiled: September 28, 2010Date of Patent: July 16, 2013Assignee: Synopsys, Inc.Inventors: Michael L. Rieger, Micheal Cranford, John P. Stirniman
-
Patent number: 8341559Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.Type: GrantFiled: November 8, 2011Date of Patent: December 25, 2012Assignee: Synopsys, Inc.Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
-
Publication number: 20120054693Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.Type: ApplicationFiled: November 8, 2011Publication date: March 1, 2012Applicant: SYNOPSYS, INC.Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
-
Patent number: 8065638Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.Type: GrantFiled: January 30, 2009Date of Patent: November 22, 2011Assignee: Synopsys, Inc.Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
-
Publication number: 20110016438Abstract: Techniques and systems for converting a non-bandlimited pattern layout into a band-limited pattern image are described. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout.Type: ApplicationFiled: September 28, 2010Publication date: January 20, 2011Applicant: SYNOPSYS, INC.Inventors: Michael L. Rieger, Micheal Cranford, John P. Stirniman
-
Patent number: 7831954Abstract: An embodiment of the present invention provides a system that computes the effect of perturbations to a pattern layout during an OPC process. During operation, the system receives a pattern layout and a set of lithography model kernels. The system then obtains a set of convolved patterns by convolving the pattern layout with each of the set of lithography model kernels. The system additionally receives a perturbation pattern to be added onto the pattern layout. Next, for a query location on the pattern layout, the system obtains a set of convolution values at the query location by using model flash lookup tables to convolve the perturbation pattern with the set of lithography model kernels. The system then updates the set of convolved patterns at the query location to account for the effect of the perturbation pattern by combining the set of convolution values with the set of convolved patterns.Type: GrantFiled: September 25, 2007Date of Patent: November 9, 2010Assignee: Synopsys, Inc.Inventors: Michael L. Rieger, Micheal Cranford, John P. Stirniman
-
Publication number: 20100198875Abstract: Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule.Type: ApplicationFiled: January 30, 2009Publication date: August 5, 2010Applicant: SYNOPSYS, INC.Inventors: Michael L. Rieger, Mathias Boman, Naji V. Bekhazi, Daniel D. Hung, Michael G. Brashler, Thomas Brett Hall
-
Patent number: 7617478Abstract: One embodiment of the present invention provides a system that converts a non-bandlimited pattern layout into a band-limited pattern image to facilitate simulating an optical lithography process. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout.Type: GrantFiled: September 25, 2007Date of Patent: November 10, 2009Assignee: Synopsys, Inc.Inventors: Michael L. Rieger, Micheal Cranford, John P. Stirniman
-
Publication number: 20090083693Abstract: Another embodiment of the present invention provides a system that computes the effect of perturbations to an input pattern layout during an OPC (Optical Proximity Correction) process. During operation, the system receives a pattern layout. The system further receives a set of lithography model kernels. The system then obtains a set of convolved patterns by convolving the pattern layout with each of the set of lithography model kernels. Next, the system computes a model flash lookup table for each of the lithography model kernels, wherein the model flash lookup table contains precomputed values for a set of convolution functions obtained by convolving a set of basis functions with the lithography model kernel. The system additionally receives a perturbation pattern to be added onto the pattern layout.Type: ApplicationFiled: September 25, 2007Publication date: March 26, 2009Applicant: SYNOPSYS, INC.Inventors: Michael L. Rieger, Micheal Cranford, John P. Stirniman
-
Publication number: 20090083692Abstract: One embodiment of the present invention provides a system that converts a non-bandlimited pattern layout into a band-limited pattern image to facilitate simulating an optical lithography process. During operation, the system receives the non-bandlimited pattern layout which comprises one or more polygons. The system further receives an anti-aliasing filter (AAF) kernel, wherein the AAF kernel is configured to convert a non-bandlimited pattern into a band-limited pattern. The system then constructs an AAF lookup table for the AAF kernel, wherein the AAF lookup table contains precomputed values for a set of convolution functions which are obtained by convolving a set of basis functions with the AAF kernel. Next, the system creates a sampled pattern layout by applying a grid map over the pattern layout. The system then obtains the band-limited pattern image by using the AAF lookup table to convolve the AAF kernel with each grid location in the sampled pattern layout.Type: ApplicationFiled: September 25, 2007Publication date: March 26, 2009Applicant: SYNOPSYS, INC.Inventors: Michael L. Rieger, Micheal Cranford, John P. Stirniman
-
Patent number: 6289499Abstract: A system for computing a pattern function for a polygonal pattern having a finite number of predetermined face angles. One method includes the steps of decomposing the polygon into a set of flashes, computing the pattern function by summing together all flashes evaluated at a point (x,y), and the pattern function returning a 1 if point (x,y) is inside a polygon and otherwise will return a 0.Type: GrantFiled: January 7, 2000Date of Patent: September 11, 2001Assignee: Avant! CorporationInventors: Michael L. Rieger, John P. Stirniman
-
Patent number: 6081658Abstract: A system for computing a pattern function for a polygonal pattern having a finite number of predetermined face angles. One method includes the steps of decomposing the polygon into a set of flashes, computing the pattern function by summing together all flashes evaluated at a point (x,y), and the pattern function returning a 1 if point (x,y) is inside a polygon and otherwise will return a 0.Type: GrantFiled: December 31, 1997Date of Patent: June 27, 2000Assignee: Avant! CorporationInventors: Michael L. Rieger, John P. Stirniman