Patents by Inventor Michael Leddige
Michael Leddige has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220139843Abstract: An integrated circuit assembly may be formed having at least one integrated circuit device electrically attached to an electronic substrate. The integrated circuit assembly may further include at least one electromagnetic interference structure attached to the electronic substrate adjacent to the at least one integrated circuit device. The at least one electromagnetic interference structure may be electrically attached to the electronic substrate with at least one resilient connector extending therebetween. In one embodiment, the at least one electromagnetic interference structure may be grounded to the electronic substrate.Type: ApplicationFiled: April 10, 2019Publication date: May 5, 2022Applicant: INTEL CORPORATIONInventors: Jun LU, Wei LIAO, Chen ZHANG, Guangying ZHANG, Liguang DU, Chuansheng LIU, Michael LEDDIGE, Weimin SHI, Eduardo MICHEL, Guillermo RENTERIA ZAMUDIO
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Patent number: 9391378Abstract: Methods and systems to support input output (IO) communications may include an IO connector having a housing with surfaces defining a paddle card region, and a set of compressible contacts extending vertically through the housing into the paddle card region. In addition, an IO interconnect can include a cable portion and at least one end portion coupled to the cable portion. The end portion may include a paddle card having a circuit board with a set of contacts disposed on a bottom surface of the circuit board. The end portion can also include an asymmetric metal shell having a configuration that encloses at least a portion of the paddle card and exposes the set of contacts.Type: GrantFiled: December 23, 2011Date of Patent: July 12, 2016Assignee: Intel CorporationInventors: Michael Leddige, Yun Ling, Kuan-Yu Chen, Kai Wang, Xiang Li, Howard Heck
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Publication number: 20140377968Abstract: Methods and systems to support input output (IO) communications may include an IO connector having a housing with surfaces defining a paddle card region, and a set of compressible contacts extending vertically through the housing into the paddle card region. In addition, an IO interconnect can include a cable portion and at least one end portion coupled to the cable portion. The end portion may include a paddle card having a circuit board with a set of contacts disposed on a bottom surface of the circuit board. The end portion can also include an asymmetric metal shell having a configuration that encloses at least a portion of the paddle card and exposes the set of contacts.Type: ApplicationFiled: December 23, 2011Publication date: December 25, 2014Inventors: Michael Leddige, Yun Ling, Kuan-Yu Chen, Kai Wang, Xiang Li, Howard Heck
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Publication number: 20140181358Abstract: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a signaling module with a receiver, quantizer, and arithmetic circuit. The receiver receives a plurality of encoded line voltages or currents on a plurality of signal lines. The quantizer determines signal levels of each of the plurality of signal lines at a unit interval. The arithmetic circuit provides a plurality of digital output bits of the decoder based on the signal levels. Each one of the digital output bits is a mathematical combination of all of the signal levels.Type: ApplicationFiled: December 28, 2013Publication date: June 26, 2014Inventors: Chaitanya Sreerama, Stephen H. Hall, Olufemi OLUWAFEMI, JASON A. Mix, Michael Leddige, Earl J. Wight, Antonio Zenteno Ramirez
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Patent number: 7772708Abstract: A stackable die mounting system with an efficient interconnect is disclosed that can have a base chip carrier to interconnect a base integrated circuit die to a circuit board on a first side and to a second stacked integrated circuit on a second side. The second side can include a first region having a pad out configuration of a first input output (I/O) to transmit data to be stored by the stacked integrated circuit die. The base chip carrier can have a second region with a pad out of a second I/O that is configured to receive data transmitted by the stacked integrated circuit die wherein the pad out of the second port is translated and rotated about an axis from the pad out of the first region such that a busses with different functions can be vertically integrated from the circuit board.Type: GrantFiled: August 31, 2006Date of Patent: August 10, 2010Assignee: Intel CorporationInventors: Michael Leddige, James A. McCall, Ajit Deosthali, Brad Larson
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Patent number: 7514773Abstract: An integrated circuit interconnection system is disclosed. The system can include a first integrated circuit die having a first electrode configuration and a second integrated die having the same or a substantially similar electrode configuration. The system can also include a multilayer flexible cable having a first side and a second side that has substantially parallel conductors running along the cable. At least a portion of one of the parallel conductors can be exposed on the first side and/or the second side, such that the first and second integrated circuit die can be connected to both the first side and the second side of the multilayer flexible cable. The cable can be folded to provide a dense interconnect for stacked memory configurations.Type: GrantFiled: August 31, 2006Date of Patent: April 7, 2009Assignee: Intel CorporationInventors: Michael Leddige, James A. McCall
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Publication number: 20080062734Abstract: A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate.Type: ApplicationFiled: September 5, 2007Publication date: March 13, 2008Inventors: Michael Leddige, Kuljit Bains, John Sprietsma
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Publication number: 20080054493Abstract: A stackable die mounting system with an efficient interconnect is disclosed that can have a base chip carrier to interconnect a base integrated circuit die to a circuit board on a first side and to a second stacked integrated circuit on a second side. The second side can include a first region having a pad out configuration of a first input output (I/O) to transmit data to be stored by the stacked integrated circuit die. The base chip carrier can have a second region with a pad out of a second I/O that is configured to receive data transmitted by the stacked integrated circuit die wherein the pad out of the second port is translated and rotated about an axis from the pad out of the first region such that a busses with different functions can be vertically integrated from the circuit board.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Inventors: Michael Leddige, James A. McCall, Ajit Deosthali, Brad Larson
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Publication number: 20080054488Abstract: An integrated circuit interconnection system is disclosed. The system can include a first integrated circuit die having a first electrode configuration and a second integrated die having the same or a substantially similar electrode configuration. The system can also include a multilayer flexible cable having a first side and a second side that has substantially parallel conductors running along the cable. At least a portion of one of the parallel conductors can be exposed on the first side and/or the second side, such that the first and second integrated circuit die can be connected to both the first side and the second side of the multilayer flexible cable. The cable can be folded to provide a dense interconnect for stacked memory configurations.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Inventors: Michael Leddige, James A. McCall
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Publication number: 20060139983Abstract: In some embodiments a memory module circuit board includes a first surface adapted to couple a first plurality of memory devices, a plurality of signal lines, and a command and address bus coupled to the signal lines. The command and address bus is routed from the signal lines and adapted to couple to at least one of the first plurality of memory devices in a manner that does not require the command and address bus lines to turn more than approximately ninety degrees before coupling to the at least one of the first plurality of memory devices. Other embodiments are described and claimed.Type: ApplicationFiled: December 23, 2004Publication date: June 29, 2006Inventors: John Sprietsma, Michael Leddige
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Publication number: 20060137903Abstract: In some embodiments a memory module circuit board includes a first layer with a first surface adapted to couple a first plurality of memory devices to the circuit board, and a second layer with a first portion and a second portion, the first portion including a plurality of first signal paths coupled to the first plurality of memory devices and the second portion including a reference voltage plane. Other embodiments are described and claimed.Type: ApplicationFiled: December 23, 2004Publication date: June 29, 2006Inventors: John Sprietsma, Michael Leddige
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Publication number: 20050195629Abstract: A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate.Type: ApplicationFiled: March 2, 2004Publication date: September 8, 2005Inventors: Michael Leddige, Kuljit Bains, John Sprietsma
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Publication number: 20050055499Abstract: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA signal is routed to a first of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal is then divided into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM. The CA signal components are then recombined and routed to the second DIMM. The recombined CA signal is then divided again into components, with each CA signal component routed serially through a group of dynamic random access memory (DRAM) chips on the first DIMM and the CA signal components are then recombined. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM.Type: ApplicationFiled: September 9, 2003Publication date: March 10, 2005Inventors: Michael Leddige, James McCall
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Publication number: 20050033905Abstract: Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA is divided on the motherboard and a CA signal component routed to each of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal component on each DIMM is then routed sequentially through each dynamic random access memory (DRAM) chip on the respective DIMM. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM. In an alternative embodiment, the CA signal is terminated on the die at the last DRAM of each respective DIMM.Type: ApplicationFiled: August 8, 2003Publication date: February 10, 2005Inventors: Michael Leddige, James McCall
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Patent number: 6111205Abstract: A connector for coupling high frequency signals between devices includes a substrate having an array of vias for coupling a reference voltage to reference voltage traces that extend along the substrate surface between the devices. Signal traces including device pads for coupling signals to and from the devices alternate with the reference voltage traces. The widths of the reference voltage traces are varied to maintain a substantially constant separation between the reference voltage trace and an adjacent signal trace.Type: GrantFiled: October 28, 1997Date of Patent: August 29, 2000Assignee: Intel CorporationInventors: Michael Leddige, John Sprietsma